Description: Designed an asynchronous clock domains between the passage of the module, and use Modelsim for simulation, the simulation results meet the intended purpose.
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File list (Check if you may need any files):
synmodule
.........\modelsim
.........\........\sysmodule
.........\........\.........\dff.vcd
.........\........\.........\dff.wlf
.........\........\.........\synmodulem.cr.mti
.........\........\.........\synmodulem.mpf
.........\........\.........\transcript
.........\........\.........\work
.........\........\.........\....\_info
.........\sysnmodule
.........\..........\Debug
.........\..........\.....\dff.obj
.........\..........\.....\main.obj
.........\..........\.....\sysnmodule.exe
.........\..........\.....\sysnmodule.ilk
.........\..........\.....\sysnmodule.pch
.........\..........\.....\sysnmodule.pdb
.........\..........\.....\vc60.idb
.........\..........\.....\vc60.pdb
.........\..........\dff.cpp
.........\..........\dff.h
.........\..........\dff.vcd
.........\..........\main.cpp
.........\..........\sysnmodule.dsp
.........\..........\sysnmodule.dsw
.........\..........\sysnmodule.ncb
.........\..........\sysnmodule.opt
.........\..........\sysnmodule.plg
.........\..........\tb.h
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