RS232_project rs232 verilog project，reciver or tra - CodeBus

Welcome！[Sign In] ！[Sign Up]！

Front-page it | Collect it | [中国-简体中文]

FAQ Fav

Location:

Embeded-SCM Develop

VHDL-FPGA-Verilog

Title: RS232_project

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
whlnkdx

Description: rs232 verilog project，reciver or trancimiter 8 bits onece

Downloaders recently: [More information of uploader whlnkdx]

To Search: verilog RS232 rs232 verilog RS232 VHDL

[uart-verilog-vhdl] - with vhdl and verilog prepared by the se
[RS232_Controller] - This project is a RS232 Controller used
[FPGA-URAT] - FPGA and the PC serial port automaticall
[uart] - uart verilog
[rs232] - Full RS232 Verilog source code, support
[UP_IP_Library_80] - altera University, IP libraries, includi

File list (Check if you may need any files):

async_receiver.v
async_transmitter.v
RS232_Controller.v

CodeBus www.codebus.net

“CodeBus” is the largest source code store in internet!

1999-2018 CodeBus All Rights Reserved.