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VHDL-FPGA-Verilog
Title:
mul
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
1kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
pbs_1987
Description:
baugh wooley multiplier with two four bit input and eight bit output
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baugh wooley
[
VHDLbasicarithmeticlibrary.Rar
] - VHDL basic arithmetic library, a very ha
[
BaughWooleyMultiplier
] - Baugh Wooley Multiplier
[
baughWooleyMultiplier
] - gate level implementation of 8*8 Signed
File list
(Check if you may need any files):
mul.v
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