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VHDL-FPGA-Verilog
Title:
float_mul_verilog
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
1 Times
Uploaded by:
gonwendon
Description:
Float Point Multiply , im verilog
Downloaders recently:
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More information of uploader gonwendon
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To Search:
ieee754
[
float_source
] -
[
float_div_verilog
] - float point div . in verilog design.
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sqrt
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VerilogProjects
] - In quartus II environment achieved with
File list
(Check if you may need any files):
mul.v ReaMe.txt
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