Description: Such as precision digital frequency meter Verilog source code, from top to bottom of design ideas, divided into six modules. Been to Altera' s FPGA boards. For your reference, hope you will not copy!
- [CPLD_pinlv] - MAXPLUS_ Cymometer environment design an
- [voltage_comp_verilog] - 8-channel to achieve high-speed analog d
- [XPS_EMC] - Xilinx EDK in SOC using external memory
- [freq_count] - simple Frequency count
- [szplj] - Digital frequency meter
- [upload] - Project 2 consists of three development
- [s3ask_ddr2] - DDR2-400 sample source code for Xilinx S
File list (Check if you may need any files):
BINtoBCD
........\BINtoBCD.asm.rpt
........\BINtoBCD.bsf
........\BINtoBCD.done
........\BINtoBCD.fit.eqn
........\BINtoBCD.fit.rpt
........\BINtoBCD.fit.summary
........\BINtoBCD.flow.rpt
........\BINtoBCD.map.eqn
........\BINtoBCD.map.rpt
........\BINtoBCD.map.summary
........\BINtoBCD.pin
........\BINtoBCD.pof
........\BINtoBCD.qpf
........\BINtoBCD.qsf
........\BINtoBCD.qws
........\BINtoBCD.sim.rpt
........\BINtoBCD.sof
........\BINtoBCD.tan.rpt
........\BINtoBCD.tan.summary
........\BINtoBCD.v
........\BINtoBCD.vwf
........\cmp_state.ini
........\db
........\..\BINtoBCD.asm.qmsg
........\..\BINtoBCD.asm_labs.ddb
........\..\BINtoBCD.cbx.xml
........\..\BINtoBCD.cmp.cdb
........\..\BINtoBCD.cmp.hdb
........\..\BINtoBCD.cmp.logdb
........\..\BINtoBCD.cmp.rdb
........\..\BINtoBCD.cmp.tdb
........\..\BINtoBCD.cmp0.ddb
........\..\BINtoBCD.db_info
........\..\BINtoBCD.eco.cdb
........\..\BINtoBCD.eds_overflow
........\..\BINtoBCD.fit.qmsg
........\..\BINtoBCD.hier_info
........\..\BINtoBCD.hif
........\..\BINtoBCD.map.cdb
........\..\BINtoBCD.map.hdb
........\..\BINtoBCD.map.logdb
........\..\BINtoBCD.map.qmsg
........\..\BINtoBCD.pre_map.cdb
........\..\BINtoBCD.pre_map.hdb
........\..\BINtoBCD.psp
........\..\BINtoBCD.rtlv.hdb
........\..\BINtoBCD.rtlv_sg.cdb
........\..\BINtoBCD.rtlv_sg_swap.cdb
........\..\BINtoBCD.sgdiff.cdb
........\..\BINtoBCD.sgdiff.hdb
........\..\BINtoBCD.signalprobe.cdb
........\..\BINtoBCD.sim.hdb
........\..\BINtoBCD.sim.qmsg
........\..\BINtoBCD.sim.rdb
........\..\BINtoBCD.sim.vwf
........\..\BINtoBCD.sld_design_entry.sci
........\..\BINtoBCD.sld_design_entry_dsc.sci
........\..\BINtoBCD.syn_hier_info
........\..\BINtoBCD.tan.qmsg
........\..\BINtoBCD_cmp.qrpt
........\..\BINtoBCD_sim.qrpt
Control
.......\cmp_state.ini
.......\Control.asm.rpt
.......\Control.bsf
.......\Control.done
.......\Control.fit.eqn
.......\Control.fit.rpt
.......\Control.fit.summary
.......\Control.flow.rpt
.......\Control.map.eqn
.......\Control.map.rpt
.......\Control.map.summary
.......\Control.pin
.......\Control.pof
.......\Control.qpf
.......\Control.qsf
.......\Control.qws
.......\Control.sim.rpt
.......\Control.sof
.......\Control.tan.rpt
.......\Control.tan.summary
.......\Control.v
.......\Control.vwf
.......\db
.......\..\Control.asm.qmsg
.......\..\Control.asm_labs.ddb
.......\..\Control.cbx.xml
.......\..\Control.cmp.cdb
.......\..\Control.cmp.hdb
.......\..\Control.cmp.logdb
.......\..\Control.cmp.rdb
.......\..\Control.cmp.tdb
.......\..\Control.cmp0.ddb
.......\..\Control.db_info
.......\..\Control.eco.cdb
.......\..\Control.eds_overflow
.......\..\Control.fit.qmsg
.......\..\Control.hier_info
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