Description: Wrote it myself, cyclic redundancy check carried out a simulation, the whole project are in!
- [encoder_and_viterbi_decoder_for(213)_convolutiona] - compressed I write for the (2,1,3) convo
- [vhdl_crc] - Quartus VHDL language used in the develo
- [Serial_CRC] - CRC checksum method of serial realize, v
- [crc] - This source code CRC5 and realize the CR
- [crc] - CRC code generator and calibration progr
- [crc16] - 16bit CRC for 8bits data
- [crc] - CRC-16 VHDL Source Code
- [crc] - crc32 to achieve the vhdl source code, h
- [CRC] - Communication systems on the circle of e
File list (Check if you may need any files):
crc
...\cmp_state.ini
...\crc.asm.rpt
...\crc.done
...\crc.fit.eqn
...\crc.fit.rpt
...\crc.fit.summary
...\crc.flow.rpt
...\crc.map.eqn
...\crc.map.rpt
...\crc.map.summary
...\crc.pin
...\crc.pof
...\crc.qpf
...\crc.qsf
...\crc.qws
...\crc.sim.rpt
...\crc.sof
...\crc.tan.rpt
...\crc.tan.summary
...\crc.vhd
...\crc.vwf
...\crc_r.vhd
...\crc_re.vhd
...\crc_s.vhd
...\crc_send.vhd
...\db
...\..\crc.asm.qmsg
...\..\crc.cbx.xml
...\..\crc.cmp.cdb
...\..\crc.cmp.hdb
...\..\crc.cmp.rdb
...\..\crc.cmp.tdb
...\..\crc.cmp0.ddb
...\..\crc.db_info
...\..\crc.eco.cdb
...\..\crc.eds_overflow
...\..\crc.fit.qmsg
...\..\crc.hier_info
...\..\crc.hif
...\..\crc.map.cdb
...\..\crc.map.hdb
...\..\crc.map.qmsg
...\..\crc.pre_map.cdb
...\..\crc.pre_map.hdb
...\..\crc.psp
...\..\crc.rpp.qmsg
...\..\crc.rtlv.hdb
...\..\crc.rtlv_sg.cdb
...\..\crc.rtlv_sg_swap.cdb
...\..\crc.sgate.rvd
...\..\crc.sgdiff.cdb
...\..\crc.sgdiff.hdb
...\..\crc.signalprobe.cdb
...\..\crc.sim.hdb
...\..\crc.sim.qmsg
...\..\crc.sim.rdb
...\..\crc.sim.vwf
...\..\crc.sld_design_entry.sci
...\..\crc.sld_design_entry_dsc.sci
...\..\crc.smp_dump.txt
...\..\crc.syn_hier_info
...\..\crc.tan.qmsg
...\..\crc_cmp.qrpt
...\..\crc_sim.qrpt
...\p2s.vhd
...\s2p.vhd
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