Description: SFF platform based on software radio, using Xilinx System Generator to achieve digital upconverter
- [ddc_simu] - Using MATLAB software radio DDC Simulati
- [ciccomp] - CIC compensation filter, applied to extr
- [VHDL] - err
- [DDC] - Verilog language implementation of the d
- [modulate_21Mc] - change the frequence uop to the one that
- [lab1] - system generator/simulink 应用开发实例,User St
- [SG] - This is the one on the System Generator
- [89346470QPSK] - system generator QPSK
File list (Check if you may need any files):
shiyan_DUC.mdl