Description: Quartus-based dual-port RAM of the integrity of the design process, including the establishment of the Engineering Simulation
- [dualportRAM] - dual-port RAM VHDL. Totally CPLD chip te
- [ram] - primitive code using VHDL prepared RAM,
- [128 × 16ram] - VHDL program designed RAM memory, dual p
- [wave_generater] - Realize four kinds of common sine wave,
- [UDLOGERV1.0back] - AT91RM9200 ping-pong algorithm for two p
- [DDS] - Based on DDS technology function wavefor
- [IDT7132LONWORKS] - At the introduction of dual-port RAM IDT
- [dual_ram] - FPGA and dual-port RAM of the DDS Arbitr
- [linuxDramDriver] - linux platform, dual-port RAM drive unde
- [Example-b4-1] - Altera basic macro functionality of the
File list (Check if you may need any files):
DupalPortRam
............\source
............\......\mixed
............\......\.....\verilog
............\......\.....\.......\mux.vhd
............\......\.....\.......\mux21.v
............\......\.....\.......\reg8.vhd
............\......\.....\.......\rotate.vhd
............\......\.....\.......\top.v
............\......\.....\vhdl
............\......\.....\....\mux.v
............\......\.....\....\mux21.vhd
............\......\.....\....\reg8.v
............\......\.....\....\rotate.v
............\......\.....\....\top.vhd
............\......\verilog
............\......\.......\ALU.V
............\......\.......\HDL_DEMO.V
............\......\VHDL
............\......\....\ALU.VHD
............\......\....\HDL_DEMO.VHD
............\Synplify_Pro
............\............\ALU_Syn_2.prd
............\............\ALU_Syn_2.prj
............\............\ALU_Syn_demo.prd
............\............\ALU_Syn_demo.prj
............\............\ALU_Syn_demo.sdc
............\............\Mix_src.prd
............\............\Mix_src_vhdl.prd
............\............\Mix_src_vhdl.prj
............\............\Mix_src_vlog.prd
............\............\Mix_src_vlog.prj
............\............\MyWorkspace.prd
............\............\MyWorkspace.prj
............\............\rev_1
............\............\.....\ALU.fse
............\............\.....\ALU.srd
............\............\.....\ALU.srm
............\............\.....\ALU.srr
............\............\.....\ALU.srs
............\............\.....\ALU.sxr
............\............\.....\ALU.tcl
............\............\.....\ALU.tlg
............\............\.....\ALU.vqm
............\............\.....\ALU.xrf
............\............\.....\ALU_cons.tcl
............\............\.....\ALU_rm.tcl
............\............\.....\AutoConstraint_alu.sdc
............\............\.....\fsmviewer.fsm
............\............\.....\HDL_DEMO.fse
............\............\.....\HDL_DEMO.srd
............\............\.....\HDL_DEMO.srm
............\............\.....\HDL_DEMO.srr
............\............\.....\HDL_DEMO.srs
............\............\.....\HDL_DEMO.sxr
............\............\.....\HDL_DEMO.ta
............\............\.....\HDL_DEMO.taq
............\............\.....\HDL_DEMO.tcl
............\............\.....\HDL_DEMO.tlg
............\............\.....\HDL_DEMO.vqm
............\............\.....\HDL_DEMO.xrf
............\............\.....\HDL_DEMO_cons.tcl
............\............\.....\HDL_DEMO_rm.tcl
............\............\.....\HDL_DEMO_ta.srm
............\............\.....\syntmp
............\............\.....\......\ALU.plg
............\............\.....\......\HDL_DEMO.plg
............\............\rev_2
............\............\.....\.recordref
............\............\.....\AutoConstraint_top.sdc
............\............\.....\layer0.tlg
............\............\.....\layer1.tlg
............\............\.....\layer2.tlg
............\............\.....\stderr.log
............\............\.....\stdout.log
............\............\.....\syntmp
............\............\.....\......\top.plg
............\............\.....\top.fse
............\............\.....\top.srd
............\............\.....\top.srm
............\............\.....\top.srr
............\............\.....\top.srs
............\............\.....\top.sxr
............\............\.....\top.tcl
............\............\.....\top.vqm
............\............\.....\top.xrf
............\............\.....\top_cons.tcl
............\............\.....\top_rm.tcl
............\............\rev_3
............\............\.....\.recordref
............\............\.....\layer0.tlg
............\............\.....\layer1.tlg
............\............\.....\layer2.tlg
............\............\.....\stderr.log
............\............\.....\stdout.log
............\............\.....\syntmp
............\............\.....\......\mux.plg
............\............\.....\......\rotate.plg
............\............\.....\......\top.plg
............\............\.....\......\top1
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