Description: 7 decoder will be translated into digital 0,1,2,3,4,5,6,7,8,9 display
To Search:
- [stop_watch] - Quartus2 prepared using electronic stopw
- [counter_clk] - Is the VHDL language, in the FPGA develo
File list (Check if you may need any files):
cmp_state.ini
db
..\deng_yimaqi.asm.qmsg
..\deng_yimaqi.cmp.cdb
..\deng_yimaqi.cmp.ddb
..\deng_yimaqi.cmp.hdb
..\deng_yimaqi.cmp.rdb
..\deng_yimaqi.cmp.tdb
..\deng_yimaqi.db_info
..\deng_yimaqi.fit.qmsg
..\deng_yimaqi.hier_info
..\deng_yimaqi.hif
..\deng_yimaqi.map.cdb
..\deng_yimaqi.map.hdb
..\deng_yimaqi.map.qmsg
..\deng_yimaqi.pre_map.hdb
..\deng_yimaqi.project.hdb
..\deng_yimaqi.rtlv.hdb
..\deng_yimaqi.rtlv_sg.cdb
..\deng_yimaqi.rtlv_sg_swap.cdb
..\deng_yimaqi.sgdiff.cdb
..\deng_yimaqi.sgdiff.hdb
..\deng_yimaqi.sim.hdb
..\deng_yimaqi.sim.qmsg
..\deng_yimaqi.sim.rdb
..\deng_yimaqi.sim.vwf
..\deng_yimaqi.sld_design_entry.sci
..\deng_yimaqi.sld_design_entry_dsc.sci
..\deng_yimaqi.syn_hier_info
..\deng_yimaqi.tan.qmsg
..\deng_yimaqi_cmp.qrpt
..\deng_yimaqi_sim.qrpt
deng_yimaqi.asm.rpt
deng_yimaqi.done
deng_yimaqi.fit.eqn
deng_yimaqi.fit.rpt
deng_yimaqi.fit.summary
deng_yimaqi.flow.rpt
deng_yimaqi.map.eqn
deng_yimaqi.map.rpt
deng_yimaqi.map.summary
deng_yimaqi.pin
deng_yimaqi.pof
deng_yimaqi.qpf
deng_yimaqi.qsf
deng_yimaqi.qws
deng_yimaqi.sim.rpt
deng_yimaqi.tan.rpt
deng_yimaqi.tan.summary
deng_yimaqi.vhd
deng_yimaqi.vwf
sim.cfg
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