Description: Realization of intel microprocessor 8088 in VHDL language, and can be tested and simulated with ModelSim.
- [USB2.0IPCore] - USB20 IP CORE, can be directly used in S
- [fftinterface] - Xinhua Cup first prize works: audio sign
- [designgamebasedonFPGA] - Run Pac-man Game Based on 8086/8088 FPGA
- [8051] - alter the company' s mcu nuclear, 805
- [27796704802_11a] - FPGA realization of an agreement to 802.
- [AteralIP] - Altera IP core of the integrity of the 8
- [i80386] - Vhdl simulation of intel s 80386 micropr
- [cpu86] - CPU86 8086. IP core.
- [8086] - 8086/8088 FPGA IP Core
File list (Check if you may need any files):
web_cpu88
.........\bin
.........\...\bin2case.exe
.........\...\bin2coe.exe
.........\...\bin2hex.exe
.........\...\bin2mem.exe
.........\copying.txt
.........\cpu86_license.txt
.........\cpu86_rtl
.........\.........\alu_rtl.vhd
.........\.........\a_table.vhd
.........\.........\biufsm_fsm.vhd
.........\.........\biu_struct.vhd
.........\.........\cpu86instr.vhd
.........\.........\cpu86pack.vhd
.........\.........\cpu86_struct.vhd
.........\.........\datapath_struct.vhd
.........\.........\dataregfile_rtl.vhd
.........\.........\divider_rtl_ser.vhd
.........\.........\d_table.vhd
.........\.........\formatter_struct.vhd
.........\.........\ipregister_rtl.vhd
.........\.........\multiplier_rtl.vhd
.........\.........\m_table.vhd
.........\.........\n_table.vhd
.........\.........\proc_rtl.vhd
.........\.........\readme.txt
.........\.........\regshiftmux_regshift.vhd
.........\.........\r_table.vhd
.........\.........\segregfile_rtl.vhd
.........\drigmorn1
.........\.........\coregen
.........\.........\.......\blk_mem_40K.ngc
.........\.........\.......\blk_mem_40K.vhd
.........\.........\.......\blk_mem_40K.xco
.........\.........\.......\coregen.cgp
.........\.........\DRIGMORN1.ucf
.........\.........\ISE
.........\.........\...\Drigmorn1
.........\.........\...\.........\alu_rtl.vhd
.........\.........\...\.........\a_table.vhd
.........\.........\...\.........\biufsm_fsm.vhd
.........\.........\...\.........\biu_struct.vhd
.........\.........\...\.........\blk_mem_40K.ngc
.........\.........\...\.........\blk_mem_40K.vhd
.........\.........\...\.........\Bootstrap_rtl.vhd
.........\.........\...\.........\cpu86instr.vhd
.........\.........\...\.........\cpu86pack.vhd
.........\.........\...\.........\cpu86_struct.vhd
.........\.........\...\.........\cpu86_top_struct.vhd
.........\.........\...\.........\datapath_struct.vhd
.........\.........\...\.........\dataregfile_rtl.vhd
.........\.........\...\.........\divider_rtl_ser.vhd
.........\.........\...\.........\Drigmorn1.ise
.........\.........\...\.........\Drigmorn1.ntrc_log
.........\.........\...\.........\Drigmorn1.restore
.........\.........\...\.........\DRIGMORN1.ucf
.........\.........\...\.........\d_table.vhd
.........\.........\...\.........\formatter_struct.vhd
.........\.........\...\.........\gh_baud_rate_gen.vhd
.........\.........\...\.........\gh_binary2gray.vhd
.........\.........\...\.........\gh_counter_down_ce_ld.vhd
.........\.........\...\.........\gh_counter_down_ce_ld_tc.vhd
.........\.........\...\.........\gh_counter_integer_down.vhd
.........\.........\...\.........\gh_DECODE_3to8.vhd
.........\.........\...\.........\gh_edge_det.vhd
.........\.........\...\.........\gh_edge_det_XCD.vhd
.........\.........\...\.........\gh_fifo_async16_rcsr_wf.vhd
.........\.........\...\.........\gh_fifo_async16_sr.vhd
.........\.........\...\.........\gh_gray2binary.vhd
.........\.........\...\.........\gh_jkff.vhd
.........\.........\...\.........\gh_parity_gen_Serial.vhd
.........\.........\...\.........\gh_register_ce.vhd
.........\.........\...\.........\gh_shift_reg_PL_sl.vhd
.........\.........\...\.........\gh_shift_reg_se_sl.vhd
.........\.........\...\.........\gh_uart_16550.vhd
.........\.........\...\.........\gh_uart_Rx_8bit.vhd
.........\.........\...\.........\gh_uart_Tx_8bit.vhd
.........\.........\...\.........\ipregister_rtl.vhd
.........\.........\...\.........\multiplier_rtl.vhd
.........\.........\...\.........\m_table.vhd
.........\.........\...\.........\n_table.vhd
.........\.........\...\.........\proc_rtl.vhd
.........\.........\...\.........\regshiftmux_regshift.vhd
.........\.........\...\.........\r_table.vhd
.........\.........\...\.........\segregfile_rtl.vhd
.........\.........\...\.........\smartpreview.twr
.........\.........\...\.........\top.ptwx
.........\.........\...\.........\top_map.map
.........\.........\...\.........\top_ngdbuild.xrpt
.........\.........\...\.........\top_summary.html
.........\.........\...\.........\top_summary.xml
.........\.........\...\.........\top_xst.xrpt
.........\.........\...\
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