Description: Used to achieve a complete VHDL code digital clock, accurate time at school, the whole point of imitation time radio.
To Search:
- [f50k] - VHDL generated clock frequency of 50 pro
- [clock] - Software development environment: ISE 7.
- [eda] - The use of VHDL language programming, bu
- [shuizhongvhdl] - When a digital clock in VHDL procedures,
- [shuzizhong2008] - When a digital clock on the VHDL program
File list (Check if you may need any files):
clock
.....\clock.asm.rpt
.....\clock.done
.....\clock.fit.rpt
.....\clock.fit.summary
.....\clock.flow.rpt
.....\clock.map.rpt
.....\clock.map.summary
.....\clock.pin
.....\clock.pof
.....\clock.qpf
.....\clock.qsf
.....\clock.qws
.....\clock.sof
.....\clock.tan.rpt
.....\clock.tan.summary
.....\clock.vhd
.....\clock.vhd.bak
.....\cnt12_24.vhd
.....\cnt12_24.vhd.bak
.....\cnt60.vhd
.....\cnt60.vhd.bak
.....\control.vhd
.....\control.vhd.bak
.....\db
.....\..\add_sub_njh.tdf
.....\..\clock.asm.qmsg
.....\..\clock.cbx.xml
.....\..\clock.cmp.cdb
.....\..\clock.cmp.hdb
.....\..\clock.cmp.logdb
.....\..\clock.cmp.rdb
.....\..\clock.cmp.tdb
.....\..\clock.cmp0.ddb
.....\..\clock.db_info
.....\..\clock.eco.cdb
.....\..\clock.fit.qmsg
.....\..\clock.hier_info
.....\..\clock.hif
.....\..\clock.map.cdb
.....\..\clock.map.hdb
.....\..\clock.map.logdb
.....\..\clock.map.qmsg
.....\..\clock.pre_map.cdb
.....\..\clock.pre_map.hdb
.....\..\clock.rpp.qmsg
.....\..\clock.rtlv.hdb
.....\..\clock.rtlv_sg.cdb
.....\..\clock.rtlv_sg_swap.cdb
.....\..\clock.sgate.rvd
.....\..\clock.sgate_sm.rvd
.....\..\clock.sgdiff.cdb
.....\..\clock.sgdiff.hdb
.....\..\clock.sld_design_entry.sci
.....\..\clock.sld_design_entry_dsc.sci
.....\..\clock.syn_hier_info
.....\..\clock.tan.qmsg
.....\..\clock.tis_db_list.ddb
.....\..\clock.tmw_info
.....\..\prev_cmp_clock.asm.qmsg
.....\..\prev_cmp_clock.fit.qmsg
.....\..\prev_cmp_clock.map.qmsg
.....\..\prev_cmp_clock.qmsg
.....\..\prev_cmp_clock.tan.qmsg
.....\led.vhd
.....\led.vhd.bak
.....\timer.vhd
.....\timer.vhd.bak
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