Description: DSP interface with the FPGA, including part of testbench, as well as the realization of
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File list (Check if you may need any files):
decode.v
decode_tb.v
dsp_port.v
dsp_port_tb.v
encode.v
encode_tb.v
main.v
main.vt
main_tb.v
r_fifo.v
s_fifo.v
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