Description: UTMI called USB2.0 Transceiver Macrocell Interface, this agreement is a signal for USB2.0-defined characteristics, is divided into 8-bit or 16-bit data interface. The purpose is to reduce the workload of developers to shorten product design cycles, reduce risk. This interface module is mainly to deal with the underlying physics of the USB protocol and signaling, can be integrated with the SIE designed a dedicated ASIC chips, can also be independent of the transceiver as a PHY chip, the next eight to PHY interface as an example to introduce the working principle and design features.
File list (Check if you may need any files):
USB2.0
......\USB2.0IP_core_Verilog
......\.....................\usb2.0.txt
......\.....................\USB2.0的IP核，包含文档和Verilog源码
......\.....................\...................................\usb_funct
......\.....................\...................................\.........\bench
......\.....................\...................................\.........\.....\CVS
......\.....................\...................................\.........\.....\...\Entries
......\.....................\...................................\.........\.....\...\Repository
......\.....................\...................................\.........\.....\...\Root
......\.....................\...................................\.........\.....\verilog
......\.....................\...................................\.........\.....\.......\CVS
......\.....................\...................................\.........\.....\.......\...\Entries
......\.....................\...................................\.........\.....\.......\...\Repository
......\.....................\...................................\.........\.....\.......\...\Root
......\.....................\...................................\.........\doc
......\.....................\...................................\.........\...\CVS
......\.....................\...................................\.........\...\...\Entries
......\.....................\...................................\.........\...\...\Repository
......\.....................\...................................\.........\...\...\Root
......\.....................\...................................\.........\...\README.txt
......\.....................\...................................\.........\...\STATUS.txt
......\.....................\...................................\.........\...\usb_doc.pdf
......\.....................\...................................\.........\rtl
......\.....................\...................................\.........\...\CVS
......\.....................\...................................\.........\...\...\Entries
......\.....................\...................................\.........\...\...\Repository
......\.....................\...................................\.........\...\...\Root
......\.....................\...................................\.........\...\verilog
......\.....................\...................................\.........\...\.......\CVS
......\.....................\...................................\.........\...\.......\...\Entries
......\.....................\...................................\.........\...\.......\...\Repository
......\.....................\...................................\.........\...\.......\...\Root
......\.....................\...................................\.........\...\.......\usbf_crc16.v
......\.....................\...................................\.........\...\.......\usbf_crc5.v
......\.....................\...................................\.........\...\.......\usbf_defines.v
......\.....................\...................................\.........\...\.......\usbf_ep_rf.v
......\.....................\...................................\.........\...\.......\usbf_ep_rf_dummy.v
......\.....................\...................................\.........\...\.......\usbf_idma.v
......\.....................\...................................\.........\...\.......\usbf_mem_arb.v
......\.....................\...................................\.........\...\.......\usbf_pa.v
......\.....................\...................................\.........\...\.......\usbf_pd.v
......\.....................\...................................\.........\...\.......\usbf_pe.v
......\.....................\...................................\.........\...\.......\usbf_pl.v
......\.....................\...................................\.........\...\.......\usbf_rf.v
......\.....................\...................................\.........\...\.......\usbf_top.v
......\.....................\..............
Download