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[Program doc] UTMI specification

Description: UTMI specification version1.05
Platform: | Size: 338512 | Author: appelping9 | Hits:

[USB develop] ehci-r10

Description:
Platform: | Size: 921600 | Author: wuyanfeng | Hits:

[Embeded-SCM Develop] Nios

Description: Nios入门实验程序问题整理 好不容易搜集起来的啊 动手才是硬道理-Nios Getting Started After finishing the experimental procedure to collect up ah hands is the last word
Platform: | Size: 182272 | Author: 谢龙飞 | Hits:

[VHDL-FPGA-Verilog] usb_phy.tar

Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Platform: | Size: 7168 | Author: eldis | Hits:

[USB develop] ULPI_v1_1

Description: 是UTMI+Low Pin Interface specifacation,适合搞USB驱动的兄弟姐妹.-UTMI+Low Pin Interface specifacation
Platform: | Size: 1189888 | Author: 何勇 | Hits:

[USB develop] ULPI_v1_0Errata

Description: 是UTMI+Low Pin Interface specifacation的错误更正,适合搞USB驱动的兄弟姐妹.-UTMI+Low Pin Interface specifacation s errata
Platform: | Size: 327680 | Author: 何勇 | Hits:

[USB develop] USB2.0

Description: UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。 -UTMI called USB2.0 Transceiver Macrocell Interface, this agreement is a signal for USB2.0-defined characteristics, is divided into 8-bit or 16-bit data interface. The purpose is to reduce the workload of developers to shorten product design cycles, reduce risk. This interface module is mainly to deal with the underlying physics of the USB protocol and signaling, can be integrated with the SIE designed a dedicated ASIC chips, can also be independent of the transceiver as a PHY chip, the next eight to PHY interface as an example to introduce the working principle and design features.
Platform: | Size: 210944 | Author: leixueyan | Hits:

[USB develop] USB2_UTMI_1_05

Description: USB2.0标准的UTMI接口，对想了解USB的IP的朋友很有帮助的-USB2.0 UTMI,GOOD DOCUMENT
Platform: | Size: 338944 | Author: 夏峰 | Hits:

[Other] utmi_1_05

Description: usb2.0 transceiver macrocell interface(UTMI) 1.05版本-usb2.0 transceiver macrocell interface (UTMI) 1.05 version of the
Platform: | Size: 338944 | Author: | Hits:

[USB develop] utmiplus_whitepaper

Description: UTMI+ for USB application development-UTMI+ for USB application development
Platform: | Size: 178176 | Author: csmr1204 | Hits:

[USB develop] UTMI_signal

Description: usb 2.0 hardware descriptor-utmi applications
Platform: | Size: 184320 | Author: Tsing Zhao | Hits:

[Program doc] Shared-Digital-Logic-of-UTMI

Description: THIS PDF MAINLY HAVING THE DOCUMENTATION OF USB UTMI LAYER ..SHARED DIGITAL LOGIC OF PHYSICAL LAYER AND ALSO CODING OF TRANCEIVER BLOCKS
Platform: | Size: 464896 | Author: venkat | Hits:

[USB develop] USB2.0

Description: USB2.0 IPCORE UTMI接口-USB2.0 IPCORE UTMI Interface
Platform: | Size: 190464 | Author: gc.wu | Hits:

[VHDL-FPGA-Verilog] usb1_funct_latest.tar

Description: USB 1.1 slave/device IP core. Default configuration is 6 endpoints: 1 Control, 1 Isochronous IN, 1, Isochronous Out, 1 Bulk IN, 1 Bulk Out, 1 Interrupt IN. Includes control engine, providing full enumeration process in hardware - no external micro-controller necessary. Derived from my USB 2.0 Function IP core, except all the high speed support logic has been ripped out and the interface was changed from shared memory to FIFO based. A basic test bench is now included as well. It should be viewed as a starting point to write a more comprehensive and complete test bench. I expect the users of this core to have some fundamental USB knowledge and be familiar with the UTMI specification and with the general USB transceivers (e.g. from philips). If you are not familiar with these two you should check out www.usb.org and read up on this subject ...
Platform: | Size: 59392 | Author: Andrey | Hits:

[Software Engineering] USB20

Description: usb2.0整体框架，主要包括SIE, PHY, UTMI模块，大部分接口也已经列在其中。-This passage introduce the structure of usb2.0, mainly include three modules(SIE, UTMI, PHY),most of the interfaces are also included.
Platform: | Size: 378880 | Author: pudn lu | Hits:

[VHDL-FPGA-Verilog] fpga_usb_serial_20131205.tar

Description: usb serial core is a vhdl synthesizable code, implementing serial data transfer over usb. Combine with a UTMI-compatible transceiver chip, this core acts as a USB device that transfers a byte stream in both directions over the bus
Platform: | Size: 253952 | Author: Doom Train | Hits:

[VHDL-FPGA-Verilog] ulpi_port

Description: ULPI UTMI conversion
Platform: | Size: 1024 | Author: CodeBase | Hits:

[Linux-Unix] clk-utmi

Description: atomic_set needs to be take the lock to protect atomic_add_unless a possible race, as it reads the counter twice:. -atomic_set needs to be take the lock to protect atomic_add_unless a possible race, as it reads the counter twice:.
Platform: | Size: 2048 | Author: gibievao | Hits:

[Linux-Unix] tegra_usb_phy

Description: utmi_pll_config_in_car_module: true if the UTMI PLL configuration registers should be set up by clk-tegra, false if by the PHY code.
Platform: | Size: 1024 | Author: nvsawl | Hits:

[VHDL-FPGA-Verilog] utmi

Description: 介绍USB PHY接口中的UTMI接口， 对使用Verilog进行USB接口编程具有帮助。(This paper introduces UTMI interface in USB PHY interface. It is helpful for programming USB interface with Verilog.)
Platform: | Size: 355328 | Author: 李秦飞 | Hits:

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