Description: -Clk_Div,- Mode_Select,-Watch,-stop_watch,-Lcd_Module,-Total_Out
source code,Simulation waveform
- [trafficlightsexperimentalreport.Rar] - VHDL traffic lights Experimental Report
- [DE2] - hard work for Dictyophora development. .
- [blank_project_0] - In nios II DE2 development board develop
- [dig-clock] - Digital clock, timing lights, can be use
- [Time] - ALTERA on DE2 platform, using internal 5
- [hex_7seg] - altera DE2 development board Verilog dig
- [watch] - VHDL design with a stopwatch functions:
- [ss] - DE2 development board sopc the developme
- [clock] - Using Verilog HDL language multi-functio
- [LCDpart] - LCD development board with altera de2 dr
File list (Check if you may need any files):
DE2.doc