Description: The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplication through the principle of each shift to achieve, from the beginning of the lowest multiplicand, if 1, then left after the multiplier and the sum of the last if for 0, left after zero-sum in full, until the highest bit multiplicand.
- [multiple] - This paper introduces some commonly used
- [comp_arith] - cpu design on the adder, multiplier, div
- [shift-mul] - In the algorithm level to realize the pr
- [VHDLshili] - The compression bag containing 4 1 PDF m
- [cf] - Multiplier features two digital signal d
- [VHDL_100_1] - 第43例 四位移位寄存器 第44例 寄存／计数器 第45例 顺序过程调用 第4
- [shifter] - 8-bit shift device to achieve arithmetic
- [multi] - pluter VHDL Quters
File list (Check if you may need any files):
移位相加8位硬件乘法器电路设计.doc
Download