VERILOG-USB2.0IP-core VERILOG language with a comp

Title: VERILOG-USB2.0IP-core

Category:
VHDL-FPGA-Verilog
Tags:
[PDF]
File Size:
215kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
wdm_zsu

Description: VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files

Downloaders recently: [More information of uploader wdm_zsu]

To Search: verilog usb2.0 in verilog usb2.0 verilog

[USB2.0code] -
[Ethernet_verilog_ip_core] - Ethernet (Ethernet) verilog ip core lang
[usb20] - Common interface usb2.0 development of t
[15-IP-core] - 15 IP cores
[fft2] - The FFT-based FPGA design, very classic,
[sdram_vhd_134] - This code is a SDRAM Controller IP Core
[DW8051] - internel ram of 8051Ip

File list (Check if you may need any files):

完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件
..............................................................\USB2.0的IP核，包含文档和Verilog源码
..............................................................\...................................\usb_funct
..............................................................\...................................\.........\bench
..............................................................\...................................\.........\.....\CVS
..............................................................\...................................\.........\.....\...\Entries
..............................................................\...................................\.........\.....\...\Repository
..............................................................\...................................\.........\.....\...\Root
..............................................................\...................................\.........\.....\verilog
..............................................................\...................................\.........\.....\.......\CVS
..............................................................\...................................\.........\.....\.......\...\Entries
..............................................................\...................................\.........\.....\.......\...\Repository
..............................................................\...................................\.........\.....\.......\...\Root
..............................................................\...................................\.........\doc
..............................................................\...................................\.........\...\CVS
..............................................................\...................................\.........\...\...\Entries
..............................................................\...................................\.........\...\...\Repository
..............................................................\...................................\.........\...\...\Root
..............................................................\...................................\.........\...\README.txt
..............................................................\...................................\.........\...\STATUS.txt
..............................................................\...................................\.........\...\usb_doc.pdf
..............................................................\...................................\.........\rtl
..............................................................\...................................\.........\...\CVS
..............................................................\...................................\.........\...\...\Entries
..............................................................\...................................\.........\...\...\Repository
..............................................................\...................................\.........\...\...\Root
..............................................................\...................................\.........\...\verilog
..............................................................\...................................\.........\...\.......\CVS
..............................................................\...................................\.........\...\.......\...\Entries
..............................................................\...................................\.........\...\.......\...\Repository
..............................................................\...................................\.........\...\.......\...\Root
..............................................................\...................................\.........\...\.......\usbf_crc16.v
..............................................................\...................................\.........\...\.......\usbf_crc5.v
............................................................

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