Description: DDS using verilog realized, can be square wave, sinusoidal and triangular
- [DDSFPGA_cylone] - dds design, spent a week doing, verilog
- [DDS51] - this program functions : DDS folder proc
- [DDS] - In Quartus using VHDL procedures for the
- [DDS-top] - Able to achieve based on the DDS output
- [sWave] - Sine wave, Verilog waveform generator, a
- [DDS] - Our group for a month to do a total of D
- [counter] - counter-microblaze......
- [ddsmodem] - modem ask, fsk, psk program susing DDS
- [MyDDS] - Prepared using look-up table method of v
- [dds] - FPGA-based DDS waveform signal generator
File list (Check if you may need any files):
dds
...\db
...\..\add_sub_hjh.tdf
...\..\dds.asm.qmsg
...\..\dds.cbx.xml
...\..\dds.cmp.cdb
...\..\dds.cmp.hdb
...\..\dds.cmp.logdb
...\..\dds.cmp.rdb
...\..\dds.cmp.tdb
...\..\dds.cmp0.ddb
...\..\dds.dbp
...\..\dds.db_info
...\..\dds.eco.cdb
...\..\dds.fit.qmsg
...\..\dds.hier_info
...\..\dds.hif
...\..\dds.map.cdb
...\..\dds.map.hdb
...\..\dds.map.logdb
...\..\dds.map.qmsg
...\..\dds.pre_map.cdb
...\..\dds.pre_map.hdb
...\..\dds.psp
...\..\dds.rtlv.hdb
...\..\dds.rtlv_sg.cdb
...\..\dds.rtlv_sg_swap.cdb
...\..\dds.sgdiff.cdb
...\..\dds.sgdiff.hdb
...\..\dds.sld_design_entry.sci
...\..\dds.sld_design_entry_dsc.sci
...\..\dds.syn_hier_info
...\..\dds.tan.qmsg
...\dds.asm.rpt
...\dds.bdf
...\dds.done
...\dds.dpf
...\dds.fit.rpt
...\dds.fit.summary
...\dds.flow.rpt
...\dds.map.rpt
...\dds.map.summary
...\dds.pin
...\dds.pof
...\dds.qpf
...\dds.qsf
...\dds.qws
...\dds.sof
...\dds.tan.rpt
...\dds.tan.summary
...\ddsmain.bsf
...\ddsmain.v
...\fangbo.bsf
...\fangbo.v
...\fangdou.bsf
...\fangdou.v
...\huo.bsf
...\huo.v
...\jcb_rom.bsf
...\jcb_rom.inc
...\jcb_rom.mif
...\jcb_rom.tdf
...\jcb_rom.v
...\jcb_rom_bb.v
...\kz.bsf
...\kz.v
...\sin_rom.bsf
...\sin_rom.inc
...\sin_rom.mif
...\sin_rom.v
...\sin_rom_bb.v
...\sjb_rom.bsf
...\sjb_rom.inc
...\sjb_rom.mif
...\sjb_rom.tdf
...\sjb_rom.v
...\sjb_rom_bb.v
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