Description: This is a VHDL prepared with adjustable duty cycle of the process, just getting started on a FPGA for the students can play a guiding role, a simple but can learn a lot
- [FPGA_27eg] - FPGA value of the 27 examples. Rar inclu
- [DAC] - Frequency, amplitude, variable duty cycl
- [xinhao001] - Generated sine wave, square wave, sawtoo
- [FRE] - vhdl
File list (Check if you may need any files):
ktf.vhd
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