Description: Written with the VERILOG pinball game, which involves the development and design VGA protocols and interfaces
To Search:
- [VGA] - FPGA to control the use of VGA display,
- [Pinball] - To achieve a 16* 16 lattice on the tri-c
- [pingball] - This is a band sound pinball game, throu
File list (Check if you may need any files):
Booth_4\booth_mul4.v
.......\tb_booth_mul4.v
.......\tb_booth_mul4_beh.prj
.......\xilinxsim.ini
.......\fuse.log
.......\isim.cmd
.......\isimwavedata.xwv
.......\tb_booth_mul4_isim_beh.wfs
.......\tb_booth_mul4.udo
.......\tb_booth_mul4.fdo
.......\tb_booth_mul4_wave.fdo
.......\transcript
.......\vsim.wlf
.......\vsim_stacktrace.vstf
.......\wlftkhw2f0
.......\wlft8bzezb
.......\booth_mul4_summary.html
.......\wlftdvn13g
.......\wlftgkc553
.......\wlftm59fdt
.......\tb_booth_mul4_isim_beh.exe
.......\t_mul_4.udo
.......\t_mul_4.fdo
.......\t_mul_4_wave.fdo
.......\wlftkrihff
.......\t_mul_4_beh.prj
.......\t_mul_4_isim_beh.wfs
.......\t_mul_4_isim_beh.exe
.......\isim.log
.......\isim.hdlsourcefiles
.......\mul_4.prj
.......\mul_4.sdc
.......\mul_4_compile.tcl
.......\mul_4_map.tcl
.......\stdout.log
.......\mul_4.htm
.......\mul_4.tlg
.......\mul_4.srs
.......\mul_4.fse
.......\mul_4.srd
.......\mul_4.srm
.......\mul_4.edn
.......\mul_4.ncf
.......\rpt_mul_4.areasrr
.......\rpt_mul_4_areasrr.htm
.......\mul_4.prd
.......\mul_4.srr
.......\Booth_4.restore
.......\Booth_4.ise
.......\verif\mul_4.vif
.......\syntmp\mul_4_flink.htm
.......\......\mul_4_srr.htm
.......\......\mul_4_toc.htm
.......\......\mul_4.plg
.......\......\mul_4.msg
.......\work\_info
.......\....\.opt1\c__modeltech_6.2b_XilinxCoreLib_ver__info
.......\....\.....\c__modeltech_6.2b_unisims_ver__info
.......\....\.....\c__modeltech_6.2b_unimacro_ver__info
.......\....\.....\work__info
.......\....\.....\work_glbl_fast.asm
.......\....\.....\work_glbl_fast.dt2
.......\....\.....\work_mul_4_fast.asm
.......\....\.....\work_mul_4_fast.dt2
.......\....\.....\work_t_mul_4_fast.asm
.......\....\.....\work_t_mul_4_fast.dt2
.......\....\.....\_deps
.......\....\t_mul_4\_primary.vhd
.......\....\.......\_primary.dat
.......\....\mul_4\_primary.vhd
.......\....\.....\_primary.dat
.......\....\_opt\c__modeltech_6.2b_XilinxCoreLib_ver__info
.......\....\....\c__modeltech_6.2b_unisims_ver__info
.......\....\....\c__modeltech_6.2b_unimacro_ver__info
.......\....\....\work__info
.......\....\....\work_glbl_fast.asm
.......\....\....\work_glbl_fast.dt2
.......\....\....\work_booth_mul4_fast.asm
.......\....\....\work_booth_mul4_fast.dt2
.......\....\....\_deps
.......\....\....\work_tb_booth_mul4_fast.asm
.......\....\....\work_tb_booth_mul4_fast.dt2
.......\....\glbl\_primary.vhd
.......\....\....\_primary.dat
.......\....\tb_booth_mul4\_primary.vhd
.......\....\.............\_primary.dat
.......\....\booth_mul4\_primary.vhd
.......\....\..........\_primary.dat
.......\isim\isimcrash.log
.......\....\simulate_dofile.log
.......\....\simulate_dofile.log_back
.......\....\isim.tmp_save\_1
.......\....\_tmp\work\m_00000000000866782574_2073120511.c
.......\....\....\....\m_00000000000866782574_2073120511.didat
.......\....\....\....\m_00000000002597385752_2104020104.c
.......\....\....\....\m_00000000002597385752_2104020104.didat
.......\....\....\....\m_00000000002597385752_2104020104.nt.obj
.......\....\....\....\m_00000000001820904209_2013589848.c
.......\....\....\....\m_00000000001820904209_2013589848.didat
.......\....\....\....\tb_booth_mul4_isim_beh.exe_lib.c
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