Description: Serial control logic to achieve VHDL source code, including various modules and components to achieve the specific cases of
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- [fpga] - Harbin institute of technology s corse.
File list (Check if you may need any files):
serial\count4.vhdl
......\ctrl.vhdl
......\decode4.vhdl
......\reg8.vhdl
......\serial.dhp
......\serial.npl
......\serial.vhdl
......\sreg.vhdl
......\__projnav
serial
ctrl\ctrl.npl
....\ctrl.vhdl
....\__projnav.log
....\automake.log
....\ctrl.prj
....\ctrl.cmd_log
....\ctrl.syr
....\ctrl.lso
....\yichu.tbw
....\coregen.log
....\coregen.prj
....\wera.tbw
....\wera.udo
....\wera.vhw
....\wera.ANT
....\wera.fdo
....\zhengque.tbw
....\yichu.vhw
....\pepExtractor.prj
....\wave.tbw
....\yichu.ANT
....\wave.vhw
....\wave.ANT
....\yichu.udo
....\yichu.fdo
....\wave.udo
....\wave.fdo
....\transcript
....\results.txt
....\zhengque.vhw
....\zhengque.ANT
....\zhengque.udo
....\zhengque.fdo
....\shujuyichu.tbw
....\shujuyichu.vhw
....\shujuyichu.ANT
....\shujuyichu.udo
....\shujuyichu.fdo
....\xiaoyancuowu.tbw
....\cuowujieshu.tbw
....\xiaoyancuowu.vhw
....\xiaoyancuowu.ANT
....\xiaoyancuowu.udo
....\xiaoyancuowu.fdo
....\cuowujieshu.udo
....\cuowujieshu.vhw
....\cuowujieshu.ANT
....\cuowujieshu.fdo
....\ctrl.stx
....\xst\work\hdllib.ref
....\...\....\sub00\vhpl00.vho
....\...\....\.....\vhpl01.vho
....\...\....\hdpdeps.ref
....\__projnav\runXst_tcl.rsp
....\.........\ctrl_flowplus.gfl
....\.........\ctrl.gfl
....\.........\ctrl.xst
....\.........\coregen.rsp
....\.........\hb_cmds
....\work\_info
....\....\ctrl\_primary.dat
....\....\....\main.dat
....\....\....\main.psm
....\....\wave\_primary.dat
....\....\....\testbench_arch.dat
....\....\....\testbench_arch.psm
....\....\ctrl_cfg\_primary.dat
....\....\........\_vhdl.psm
....\....\.uowujieshu\_primary.dat
....\....\...........\testbench_arch.dat
....\....\...........\testbench_arch.psm
....\....\www\_primary.dat
....\....\...\testbench_arch.dat
....\....\...\testbench_arch.psm
....\....\.era\_primary.dat
....\....\....\testbench_arch.dat
....\....\....\testbench_arch.psm
....\....\yichu\_primary.dat
....\....\.....\testbench_arch.dat
....\....\.....\testbench_arch.psm
....\....\zhengque\_primary.dat
....\....\........\testbench_arch.dat
....\....\........\testbench_arch.psm
....\....\shujuyichu\_primary.dat
....\....\..........\testbench_arch.dat
....\....\..........\testbench_arch.psm
....\....\xiaoyancuowu\_primary.dat
....\....\............\testbench_arch.dat
....\....\............\testbench_arch.psm
....\vsim.wlf
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