Description: CPLD study, using VHDL, application EPM7032, one of the routines 138,373, and 273
- [codeofvhdl2006] - [ Classics design ] the VHDL source cod
- [2x8bit_dac] - With EPM7032 (CPLD) to do 2-way 8-bit pa
- [bpsk] - Based on the vhdl language bpsk programm
- [bysj] - VHDL hardware language with BPSK modulat
- [EPM7032] - VHDL语言以及ByteBlaster在线可编程技术来实现自动交通控制系统的方法
File list (Check if you may need any files):
counter-CPLD\LIB.DLS
............\shu.acf
............\shu.fit
............\shu.hif
............\shu.jam
............\shu.jbc
............\shu.mmf
............\shu.ndb
............\shu.pin
............\shu.pof
............\shu.rpt
............\shu.snf
............\SHU.sym
............\shu.vhd
............\shubi.acf
............\shubi.fit
............\shubi.hif
............\shubi.jam
............\shubi.jbc
............\shubi.mmf
............\shubi.ndb
............\shubi.pin
............\shubi.pof
............\shubi.rpt
............\shubi.snf
............\SHUBI.sym
............\shubi.vhd
............\U0524622.DLS
............\U4576772.DLS
............\U6900018.DLS
............\U9073764.DLS
............\U9401646.DLS
............\U9961038.DLS
counter-CPLD
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