Description: : ISE5.1i is a Xilinx introduced a ASIC-strength design tools, which fully exploit the Virtex Ⅱ Pro series chip' s potential Virtex-II Pro series of chip gate density of 40,000 to 8,000,000 from the door. Compared with the 4.1i, the designer at compile time, the time spent has been improved several times (from 100,000/min to 200,000 gate/min) and in the device speed increase of 40 .
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