Title:
AReconfigurableFIRFilterSystemBasedonFPGA
Download
Description: In this dissertation，a reconfigurable FIR filter system based on FPGA is designed，which combine high—speed operation of FPGA and flexibility of computer using USB2．0 interface．According to the filter specialties，the filter coefficients are calculated by the computer．And the configured coefficients of the multistage FIR filter are downloaded to the chip．The filtering computing is completed by the FPGA．The filtered data iS transmitted to the computer through the USB2．0 interface for further processing，such as displaying，analyzing and storing．The states conversion between coefficients configuring mode and filtering mode is finished by FSM(Finite State Machine)，which ensures the system to work orderly．
- [usb_2] - Usb2 FPGA implementation, verilog statem
- [fir] - Completion of a FIR digital filter desig
- [FCUSB-CY7C68013-56] - 68013 development board user manual, det
- [dso] - The design of the chip as a high-speed s
- [fpga_data] - fpga multi-channel
- [decoder] - Instruction decoder design vhdl language
- [RC] - Flexibility of both software and hardwar
File list (Check if you may need any files):
A Reconfigurable FIR Filter System Based on FPGA.pdf
