Description: Realize the filter function, finite impulse response (FIR) digital filters and infinite impulse response (IIR) digital filters are widely used in digital signal processing systems. IIR digital filter to facilitate simple, but it is non-linear phase to adopt the all-pass network phase correction, and the stability can not be guaranteed. FIR filter has a good linear phase characteristics, making it more and more widely appreciated.
- [iir_rtl] - Sipmple iir digital filter
- [IIR] - Experiment description: this experiment
- [lp_iir_filter_latest.tar] - iir filter for dsp processing
- [filter1] - Entitled based on CSD code FIR digital f
- [iir_filter] - iir filter fpga implementation, teach yo
- [FPGA_FIR] - FPGA-based FIR filter' s source code,
File list (Check if you may need any files):
fir_filter\add121313.bsf
..........\add121313.vhd
..........\add121414.bsf
..........\add121414.vhd
..........\add141616.bsf
..........\add888.bsf
..........\add888.vhd
..........\add889.bsf
..........\add889.vhd
..........\cmp_state.ini
..........\db\add_sub_0ph.tdf
..........\..\add_sub_1ph.tdf
..........\..\add_sub_2ph.tdf
..........\..\add_sub_3ph.tdf
..........\..\add_sub_4ph.tdf
..........\..\add_sub_knh.tdf
..........\..\add_sub_lnh.tdf
..........\..\add_sub_voh.tdf
..........\..\fir-sim.vwf
..........\..\fir.cbx.xml
..........\..\fir.cmp.rdb
..........\..\fir.dbp
..........\..\fir.db_info
..........\..\fir.eco.cdb
..........\..\fir.eds_overflow
..........\..\fir.fnsim.cdb
..........\..\fir.fnsim.hdb
..........\..\fir.fnsim.qmsg
..........\..\fir.hier_info
..........\..\fir.hif
..........\..\fir.map.cdb
..........\..\fir.map.hdb
..........\..\fir.map.logdb
..........\..\fir.map.qmsg
..........\..\fir.pre_map.cdb
..........\..\fir.pre_map.hdb
..........\..\fir.psp
..........\..\fir.pss
..........\..\fir.rpp.qmsg
..........\..\fir.rtlv.hdb
..........\..\fir.rtlv_sg.cdb
..........\..\fir.rtlv_sg_swap.cdb
..........\..\fir.sgate.rvd
..........\..\fir.sgate_sm.rvd
..........\..\fir.sgdiff.cdb
..........\..\fir.sgdiff.hdb
..........\..\fir.sim.cvwf
..........\..\fir.sim.hdb
..........\..\fir.sim.qmsg
..........\..\fir.sim.rdb
..........\..\fir.simfam
..........\..\fir.sld_design_entry.sci
..........\..\fir.sld_design_entry_dsc.sci
..........\..\fir.syn_hier_info
..........\..\fir.tis_db_list.ddb
..........\..\fir_cmp.qrpt
..........\..\fir_hier_info
..........\..\fir_sim.qrpt
..........\..\fir_syn_hier_info
..........\..\prev_cmp_fir.map.qmsg
..........\..\prev_cmp_fir.qmsg
..........\..\wed.wsf
..........\db
..........\dff8.bsf
..........\dff8.vhd
..........\dff89.bsf
..........\fir.asm.rpt
..........\fir.bdf
..........\fir.bsf
..........\fir.done
..........\fir.fit.eqn
..........\fir.fit.rpt
..........\fir.flow.rpt
..........\fir.map.eqn
..........\fir.map.rpt
..........\fir.map.summary
..........\fir.pin
..........\fir.pof
..........\fir.qpf
..........\fir.qsf
..........\fir.qws
..........\fir.sim.rpt
..........\fir.sof
..........\fir.tan.rpt
..........\fir.tan.summary
..........\fir.vhd
..........\fir.vwf
..........\fir_assignment_defaults.qdf
..........\mult12.bsf
..........\mult12.vhd
..........\mult13.bsf
..........\mult13.vhd
..........\mult14.bsf
..........\mult14.vhd
..........\mult162.bsf
..........\mult162.vhd
..........\mult18.bsf
..........\mult18.vhd
..........\mult242.bsf
..........\mult242.vhd
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