Description: VHDL course experiment 6, NC Divider. Corresponding to different input signals, the set value (initial count) to set a different value, preset counter this initial state the number of different values of the count mode, when the state of the counter are all 1, the counter overflow output signal. With the counter overflow signal as the output signal or output signal of the control value, the output signal frequency is controlled by the preset number of input
To Search:
- [nfenpin] - N divider is a simple addition to N coun
File list (Check if you may need any files):
experiment6\DVF.vhd
...........\DVF.qpf
...........\DVF.qsf
...........\DVF.map.eqn
...........\DVF.map.rpt
...........\DVF.flow.rpt
...........\DVF.map.summary
...........\DVF.fit.eqn
...........\DVF.pin
...........\DVF.fit.rpt
...........\DVF.fit.summary
...........\DVF.sof
...........\DVF.pof
...........\DVF.asm.rpt
...........\DVF.tan.summary
...........\DVF.tan.rpt
...........\DVF.done
...........\DVF.vwf
...........\DVF.sim.rpt
...........\DVF.cdf
...........\DVF.qws
...........\cmp_state.ini
...........\DVF_assignment_defaults.qdf
...........\DVF.fit.smsg
...........\DVF.jpg
...........\RLTOFDVF.jpg
...........\db\DVF_cmp.qrpt
...........\..\wed.zsf
...........\..\DVF_sim.qrpt
...........\..\DVF.db_info
...........\..\DVF.map.qmsg
...........\..\DVF.cbx.xml
...........\..\DVF.hif
...........\..\DVF.hier_info
...........\..\DVF.rtlv_sg.cdb
...........\..\DVF.rtlv.hdb
...........\..\DVF.rtlv_sg_swap.cdb
...........\..\DVF.pre_map.hdb
...........\..\DVF.pre_map.cdb
...........\..\DVF.psp
...........\..\DVF.dbp
...........\..\DVF.map.logdb
...........\..\DVF.sgdiff.cdb
...........\..\DVF.sgdiff.hdb
...........\..\DVF.sld_design_entry_dsc.sci
...........\..\DVF.syn_hier_info
...........\..\DVF.map.cdb
...........\..\DVF.map.hdb
...........\..\DVF.fit.qmsg
...........\..\DVF.cmp.logdb
...........\..\DVF.cmp.kpt
...........\..\DVF.asm.qmsg
...........\..\DVF.tan.qmsg
...........\..\DVF.cmp.tdb
...........\..\DVF.cmp0.ddb
...........\..\DVF.cmp.cdb
...........\..\DVF.signalprobe.cdb
...........\..\DVF.cmp.hdb
...........\..\DVF.cmp.rdb
...........\..\DVF.rpp.qmsg
...........\..\DVF.sgate.rvd
...........\..\DVF.sgate_sm.rvd
...........\..\DVF.eds_overflow
...........\..\DVF.sim.qmsg
...........\..\DVF.sim.hdb
...........\..\DVF.sim.vwf
...........\..\DVF.sim.rdb
...........\..\DVF.sld_design_entry.sci
...........\..\DVF.eco.cdb
...........\db
experiment6
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