File list (Check if you may need any files):
README
vhdl\bitreg.vhd
....\bytereg.vhd
....\clk_div.vhd
....\crcreg.vhd
....\jcounter.vhd
....\onewire_iface.vhd
....\onewire_iface_syn.prj
....\onewire_master.vhd
....\shreg.vhd
....\TEST_ONEWIRE_IFACE.DO
....\TEST_ONEWIRE_IFACE.VHD
vhdl
.erilog\bitreg.v
.......\clk_div.v
.......\crcreg.v
.......\defines.v
.......\glbl.v
.......\jcnt1.v
.......\jcnt2.v
.......\onewire_iface.v
.......\onewire_iface_syn.prj
.......\onewire_master.v
.......\parallel_sn_data.v
.......\sr1.v
.......\sr2.v
.......\TEST_NO_SLAVE.do
.......\TEST_NO_SLAVE.v
.......\TEST_ONEWIRE_WITH_BAD_CRC.do
.......\TEST_ONEWIRE_WITH_BAD_CRC.v
.......\TEST_ONEWIRE_WITH_VALID_CRC.do
.......\TEST_ONEWIRE_WITH_VALID_CRC.v
.......\TEST_SLAVE_PRESENT.do
.......\TEST_SLAVE_PRESENT.v
verilog
xapp198[1].pdf
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