Description: Using verilog language, achieve DS18B20 temperature measurement procedures, and including the project file.
- [verilog] - Verilog design example, a very detailed
- [eth_interface] - FPGA-based Ethernet interface. Use: 1. C
- [ds18b20] - Single DS18B20 the verilog HDL code, and
- [ds18b20s16] - 16 DS18B20 the verilog HDL code, and an
- [LCD12864] - 1 fpga driver' s verilog source code
File list (Check if you may need any files):
ds18b20_top\ds18b20_top.qpf
...........\ds18b20_top.qsf
...........\ds18b20_top.bdf
...........\clk_div.v
...........\ds18b20_top.qws
...........\ds18b20_top.map.rpt
...........\ds18b20_top.flow.rpt
...........\ds18b20_top.map.summary
...........\ds18b20_top.done
...........\clk_div.bsf
...........\temperature.v
...........\temperature.bsf
...........\Two_to_ten.v
...........\db\ds18b20_top.db_info
...........\..\ds18b20_top.cbx.xml
...........\..\ds18b20_top.hif
...........\..\ds18b20_top.hier_info
...........\..\ds18b20_top.psp
...........\..\ds18b20_top.pss
...........\..\ds18b20_top.dbp
...........\..\ds18b20_top.analyze_file.qmsg
...........\..\ds18b20_top.syn_hier_info
...........\..\ds18b20_top.rtlv_sg.cdb
...........\..\ds18b20_top.rtlv.hdb
...........\..\ds18b20_top.rtlv_sg_swap.cdb
...........\..\ds18b20_top.pre_map.hdb
...........\..\ds18b20_top.pre_map.cdb
...........\..\ds18b20_top.smp_dump.txt
...........\..\ds18b20_top.map.logdb
...........\..\ds18b20_top.sgdiff.cdb
...........\..\ds18b20_top.sgdiff.hdb
...........\..\ds18b20_top.sld_design_entry_dsc.sci
...........\..\ds18b20_top.map.cdb
...........\..\ds18b20_top.map.hdb
...........\..\ds18b20_top.cmp.rdb
...........\..\ds18b20_top.sld_design_entry.sci
...........\..\ds18b20_top.eco.cdb
...........\..\ds18b20_top.map.qmsg
...........\db
ds18b20_top
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