Xil3SD1800A_MIG\datasheet.txt
...............\log.txt
...............\par\create_ise.bat
...............\...\icon_coregen.xco
...............\...\ila_coregen.xco
...............\...\ise_flow.bat
...............\...\ise_run.txt
...............\...\mem_interface_top.ut
...............\...\MIG_new.ucf
...............\...\readme.txt
...............\...\set_ise_prop.txt
...............\...\vio_coregen.xco
...............\rtl\MIG_new.vhd
...............\...\MIG_new_cal_ctl.vhd
...............\...\MIG_new_cal_top.vhd
...............\...\MIG_new_clk_dcm.vhd
...............\...\MIG_new_controller_0.vhd
...............\...\MIG_new_controller_iobs_0.vhd
...............\...\MIG_new_data_path_0.vhd
...............\...\MIG_new_data_path_iobs_0.vhd
...............\...\MIG_new_data_read_0.vhd
...............\...\MIG_new_data_read_controller_0.vhd
...............\...\MIG_new_data_write_0.vhd
...............\...\MIG_new_dqs_delay_0.vhd
...............\...\MIG_new_fifo_0_wr_en_0.vhd
...............\...\MIG_new_fifo_1_wr_en_0.vhd
...............\...\MIG_new_infrastructure.vhd
...............\...\MIG_new_infrastructure_iobs_0.vhd
...............\...\MIG_new_infrastructure_top.vhd
...............\...\MIG_new_iobs_0.vhd
...............\...\MIG_new_parameters_0.vhd
...............\...\MIG_new_ram8d_0.vhd
...............\...\MIG_new_rd_gray_cntr.vhd
...............\...\MIG_new_s3_dm_iob.vhd
...............\...\MIG_new_s3_dqs_iob.vhd
...............\...\MIG_new_s3_dq_iob.vhd
...............\...\MIG_new_tap_dly.vhd
...............\...\MIG_new_top_0.vhd
...............\...\MIG_new_wr_gray_cntr.vhd
...............\sim\ddr2_model.v
...............\...\ddr2_model.v.bak
...............\...\ddr2_model_parameters.vh
...............\...\glbl.v
...............\...\MIG_new_addr_gen_0.vhd
...............\...\MIG_new_cmd_fsm_0.vhd
...............\...\MIG_new_cmp_data_0.vhd
...............\...\MIG_new_data_gen_0.vhd
...............\...\MIG_new_test_bench_0.vhd
...............\...\sim.do
...............\...\sim.exe
...............\...\simulation_help.chm
...............\...\sim_log.txt
...............\...\sim_tb_top.vhd
...............\...\transcript
...............\...\wiredly.vhd
...............\...\.ork\ddr2_model\verilog.asm
...............\...\....\..........\verilog.rw
...............\...\....\..........\_primary.dat
...............\...\....\..........\_primary.dbs
...............\...\....\..........\_primary.vhd
...............\...\....\glbl\verilog.asm
...............\...\....\....\verilog.rw
...............\...\....\....\_primary.dat
...............\...\....\....\_primary.dbs
...............\...\....\....\_primary.vhd
...............\...\....\mig_new\arc_mem_interface_top.asm
...............\...\....\.......\arc_mem_interface_top.dat
...............\...\....\.......\arc_mem_interface_top.dbs
...............\...\....\.......\arc_mem_interface_top.rw
...............\...\....\.......\_primary.dat
...............\...\....\.......\_primary.dbs
...............\...\....\......._addr_gen_0\arc.asm
...............\...\....\..................\arc.dat
...............\...\....\..................\arc.dbs
...............\...\....\..................\arc.rw
...............\...\....\..................\_primary.dat
...............\...\....\..................\_primary.dbs
...............\...\....\........cal_ctl\arc_cal_ctl.asm
...............\...\....\...............\arc_cal_ctl.dat
...............\...\....\...............\arc_cal_ctl.dbs
...............\...\....\...............\arc_cal_ctl.rw
...............\...\....\...............\_primary.dat
...............\...\....\...............\_primary.dbs
...............\...\....\............top\arc.asm
...............\...\....\...............\arc.dat
...............\...\....\...............\arc.dbs
...............\...\....\...............\arc.rw
...............\...\....\...............\_primary.dat
...............\...\....\...............\_primary.dbs
...............\...\....\.........lk_dcm\arc.asm
...............\...\....\...............\arc.dat
...............\...\....\...............\arc.dbs
...............\...\....\....