CY7c68013_fpga_write_sram\FPGA\automake.log
.........................\....\bitgen.ut
.........................\....\coregen.log
.........................\....\coregen.prj
.........................\....\FPGA.dhp
.........................\....\FPGA.npl
.........................\....\prom.mcs
.........................\....\prom.prm
.........................\....\prom.sig
.........................\....\top(读flag另为一个状态).vhdl
.........................\....\top.bgn
.........................\....\top.bit
.........................\....\top.bld
.........................\....\top.cmd_log
.........................\....\top.drc
.........................\....\top.ll
.........................\....\top.lso
.........................\....\top.mrp
.........................\....\top.msd
.........................\....\top.msk
.........................\....\top.nc1
.........................\....\top.ncd
.........................\....\top.ngc
.........................\....\top.ngd
.........................\....\top.ngm
.........................\....\top.ngr
.........................\....\top.pad
.........................\....\top.pad_txt
.........................\....\top.par
.........................\....\top.pcf
.........................\....\top.placed_ncd_tracker
.........................\....\top.prj
.........................\....\top.rbb
.........................\....\top.rbd
.........................\....\top.routed_ncd_tracker
.........................\....\top.stx
.........................\....\top.syr
.........................\....\top.twr
.........................\....\top.twx
.........................\....\top.ut
.........................\....\top.vhdl
.........................\....\top.xpi
.........................\....\top_1.vhdl
.........................\....\top_2.vhdl
.........................\....\top_last_par.ncd
.........................\....\top_map.ncd
.........................\....\top_map.ngm
.........................\....\top_pad.csv
.........................\....\top_pad.txt
.........................\....\ucf.ucf
.........................\....\ucf.ucf.untf
.........................\....\xst\work\hdllib.ref
.........................\....\...\....\hdpdeps.ref
.........................\....\...\....\sub00\vhpl00.vho
.........................\....\...\....\.....\vhpl01.vho
.........................\....\_impact.cmd
.........................\....\_impact.log
.........................\....\.ngo\netlist.lst
.........................\....\._projnav\bitgen.rsp
.........................\....\.........\coregen.rsp
.........................\....\.........\ednTOngd_tcl.rsp
.........................\....\.........\FPGA.gfl
.........................\....\.........\FPGA_flowplus.gfl
.........................\....\.........\map.log
.........................\....\.........\nc1TOncd_tcl.rsp
.........................\....\.........\par.log
.........................\....\.........\parentEditConstraintsTextApp_tcl.rsp
.........................\....\.........\posttrc.log
.........................\....\.........\runXst_tcl.rsp
.........................\....\.........\top.xst
.........................\....\.........\top_ncdTOut_tcl.rsp
.........................\....\__projnav.log
.........................\....\xst\work\sub00
.........................\....\...\work
.........................\....\xst
.........................\....\_ngo
.........................\....\__projnav
.........................\FPGA
CY7c68013_fpga_write_sram