fifo implementation using Verilog hdl usb, this is

Title: fifo

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
6kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
zhulyan580086

Description: implementation using Verilog hdl usb, this is a common source, the document had a very detailed notes, beginners should understand.

Downloaders recently: [More information of uploader zhulyan580086]

To Search: Verilog USB fifo usb verilog document

[usb_verilog.tar] - document contains a usb ASIC design, the
[USB_I2C_MAC_FPGA_Code] - FPGA digital electronic system design an
[FIFO] - a comprehensive Verilog can write FIFO m
[AlteraSDR-SDRAM] - SDRAM controller provided by Altera in V
[usb11] - Verilog HDL based on a USB 1.1 of the IP
[Memory] - Example of a FIFO code in verilog langua
[USB] - Verilog implementation USB program, open
[NIOS_USB_API_demo] - In the nios system development driver us
[AsynchronousFIFOArchitectures-CN] - AsynchronousFIFOArchitectures, this clas
[source_code] - verilog code fifo memory usb

File list (Check if you may need any files):

fifo_test\beh_fifo.v
.........\fifo1.v
.........\fifomem.v
.........\log_out.txt
.........\rptr_empty.v
.........\sync_r2w.v
.........\sync_w2r.v
.........\wave.do
.........\wptr_full.v
fifo_test

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