Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: ALU Download
 Description: Arithmetic logic unit of the verilog code, it can achieve half adder, full adder, compare, bitwise and, bitwise or, bitwise xor, plus one, minus one operation
 Downloaders recently: [More information of uploader shashalpf]
 To Search: verilog code for alu ALU
File list (Check if you may need any files): 
ALU.doc

CodeBus www.codebus.net