Description: String and convert the signal to make it into I, Q2 output signal
To Search:
- [S2P_xapp194] - VHDL, verilog Series and conversion comp
- [ctos] - Use vhdl complete spartan3E development
- [68140323] - vhdl realized and string conversion, and
File list (Check if you may need any files):
FPGA中关于串并变换.doc