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Title: Example Download
 Description: FPGA Projects example in ISE environment, it s very useful
 Downloaders recently: [More information of uploader lwl_306]
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Example\cntr_rtl.v
.......\cntr_struct.v
.......\modelsim.ini
.......\Source\cntr_rtl.v
.......\......\cntr_struct.v
.......\......\stimulus.do
.......\stimulus.do
.......\vsim.wlf
.......\work\cntr_rtl\verilog.asm
.......\....\........\_primary.dat
.......\....\........\_primary.vhd
.......\....\_info
.......\....\cntr_rtl
.......\....\_temp
.......\Source
.......\work
Example
    

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