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VHDL-FPGA-Verilog
Title:
MII_timing
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Category:
VHDL-FPGA-Verilog
Tags:
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
huihui5ritt
Description:
implementation of MII data transmission’s timing control
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File list
(Check if you may need any files):
用FPGA实现MII的数据传送时序控制\mdio_module.vhd 用FPGA实现MII的数据传送时序控制
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