基于wishbone总线的UART IP core\raminfr.v
..............................\timescale.v
..............................\transcript
..............................\uart_defines.v
..............................\uart_receiver.v
..............................\uart_regs.v
..............................\uart_rfifo.v
..............................\uart_tfifo.v
..............................\uart_top.v
..............................\uart_transmitter.v
..............................\uart_wb.v
..............................\wb_mast.v
基于wishbone总线的UART IP core