Description: DCT-FPGA, with the verilog language to the fast DCT algorithm, which is LOEFFLER algorithm that out.
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File list (Check if you may need any files):
dct\automake.log
...\coregen.log
...\coregen.prj
...\dct.cmd_log
...\dct.dhp
...\dct.lso
...\dct.ngc
...\dct.ngr
...\dct.npl
...\dct.prj
...\dct.stx
...\dct.syr
...\dct.v
...\dct_dct_t2_v_tf.fdo
...\dct_dct_t2_v_tf.udo
...\dct_t2.v
...\dct_vhdl.prj
...\multiplier.cmd_log
...\multiplier.lso
...\multiplier.ngc
...\multiplier.ngr
...\multiplier.prj
...\multiplier.stx
...\multiplier.syr
...\multiplier_vhdl.prj
...\transcript
...\vsim.wlf
...\work\dct\verilog.asm
...\....\...\_primary.dat
...\....\...\_primary.vhd
...\....\dct
...\....\..._dct_t2_v_tf\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\dct_dct_t2_v_tf
...\....\.........3_v_tf\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\dct_dct_t3_v_tf
...\....\........._v_tf\verilog.asm
...\....\..............\_primary.dat
...\....\..............\_primary.vhd
...\....\dct_dct_t_v_tf
...\....\glbl\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\glbl
...\....\multiplier\verilog.asm
...\....\..........\_primary.dat
...\....\..........\_primary.vhd
...\....\multiplier
...\....\_info
...\work
...\xst\work\hdllib.ref
...\...\....\vlg27\dct.bin
...\...\....\vlg27
...\...\....\...7B\multiplier.bin
...\...\....\vlg7B
...\...\work
...\xst
...\__projnav\coregen.rsp
...\.........\createTF.err
...\.........\dct.gfl
...\.........\dct.xst
...\.........\dct_flowplus.gfl
...\.........\multiplier.xst
...\.........\runXst_tcl.rsp
...\__projnav
...\__projnav.log
dct
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