Description: This file is the 2009 National Undergraduate Electronic Design Contest figures the number of amplitude-frequency balanced power amplifier part of the project documents, including the modelsim simulation part.
To Search:
- [zaiTSPv] - ADI contest this year I participated in
- [fir] - VHDL language with my own series of 16-o
- [jingsai] - National Undergraduate Electronic Design
- [equalization] - Digital audio signal of the amplitude-fr
- [9850] - To participate in Electronic Design Cont
- [source] - This procedure for the 2009 " NEC&qu
- [jingsai] - This is our participation in 2009 the na
- [FIR-filter-using-fpga-design] - FIR using FPGA ，QuartusII software
- [qtopia-book] - This book is a Linux environment for the
- [voice_data_collector] - Electronic Design Competition sample que
File list (Check if you may need any files):
fpga_balance_project\modelsim(backup)\balance.v
....................\................\balance.v.bak
....................\................\balance_top.cr.mti
....................\................\balance_top.mpf
....................\................\balance_top.v
....................\................\balance_top.v.bak
....................\................\multiply.v
....................\................\tcl_stacktrace.txt
....................\................\top_balance.xml
....................\................\top_balance_tb.v
....................\................\top_balance_tb.v.bak
....................\................\vsim.wlf
....................\................\work\balance\verilog.asm
....................\................\....\.......\_primary.dat
....................\................\....\.......\_primary.vhd
....................\................\....\multiply\verilog.asm
....................\................\....\........\_primary.dat
....................\................\....\........\_primary.vhd
....................\................\....\top_balance\verilog.asm
....................\................\....\...........\_primary.dat
....................\................\....\...........\_primary.vhd
....................\................\....\..........._tb\verilog.asm
....................\................\....\..............\_primary.dat
....................\................\....\..............\_primary.vhd
....................\................\....\_info
....................\................\....\balance
....................\................\....\multiply
....................\................\....\top_balance
....................\................\....\top_balance_tb
....................\................\work
....................\modelsim(backup)
fpga_balance_project
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