Description: Includes image acquisition, i2c design and mixed-language simulation, DDR controller, and a number of small programs for learning to use
- [newboardconfig] - cyclone II 208c8 prepared display image
- [DDR] - DDR SDRAM on detailed principles and tim
- [sdram32] - DDR SDRAM source verilog source codes
- [Chapter10Sample] - vidio and miage tacking with the verilog
- [color_conv] - BT656, YCBCR data format converted into
- [h264_intp] - H264 graphic image interpolation algorit
- [DDRSDRAM_VHDL] - Enclosing the doc is a DDR SDRAM referen
- [FIFO_Asyn] - Source code for asyn_fifo using verilog
- [YAFFS_Direct_User_Guide] - The user guide of YAFFS Direct. It docum
- [DDRcontrol] - DDR controller design for reference, inc
File list (Check if you may need any files):
adder8\adder8.cmd_log
......\adder8.dhp
......\adder8.ise
......\adder8.ise_ISE_Backup
......\adder8.lso
......\adder8.ngc
......\adder8.ngr
......\adder8.prj
......\adder8.stx
......\adder8.syr
......\adder8.vhd
......\adder8_summary.html
......\adder_t.vhd
......\adder_tt_vhd.fdo
......\adder_tt_vhd.udo
......\adder_t_vhd.fdo
......\adder_t_vhd.udo
......\automake.log
......\pepExtractor.prj
......\Project.dhp
......\results.txt
......\transcript
......\Untitled-1
......\userlang.tpl
......\values.txt
......\work\adder8\behavioral.asm
......\....\......\behavioral.dat
......\....\......\_primary.dat
......\....\....._tt_vhd\behavior.asm
......\....\............\behavior.dat
......\....\............\_primary.dat
......\....\......._vhd\_primary.dat
......\....\_info
......\xst\work\hdllib.ref
......\...\....\hdpdeps.ref
......\...\....\sub00\vhpl00.vho
......\...\....\.....\vhpl01.vho
......\__projnav\adder8.gfl
......\.........\adder8.xst
......\.........\adder8_flowplus.gfl
......\.........\runXst_tcl.rsp
......\.........\sumrpt_tcl.rsp
......\__projnav.log
...in\add4in.cmd_log
.....\add4in.lso
.....\add4in.ngc
.....\add4in.ngr
.....\add4in.prj
.....\add4in.stx
.....\add4in.syr
.....\add4in.vhd
.....\add4in_add_tb_vhd_tb.fdo
.....\add4in_add_tb_vhd_tb.udo
.....\addin.dhp
.....\addin.npl
.....\add_tb.vhd
.....\automake.log
.....\coregen.log
.....\coregen.prj
.....\pepExtractor.prj
.....\textdata.dat
.....\transcript
.....\vsim.wlf
.....\work\add4in\behavioral.asm
.....\....\......\behavioral.dat
.....\....\......\_primary.dat
.....\....\......_add_tb_vhd_tb\behavior.asm
.....\....\....................\behavior.dat
.....\....\....................\_primary.dat
.....\....\_info
.....\xst\work\hdllib.ref
.....\...\....\hdpdeps.ref
.....\...\....\sub00\vhpl00.vho
.....\...\....\.....\vhpl01.vho
.....\__projnav\add4in.xst
.....\.........\addin.gfl
.....\.........\addin_flowplus.gfl
.....\.........\coregen.rsp
.....\.........\runXst_tcl.rsp
.....\__projnav.log
caiji\caiji.cmd_log
.....\caiji.dhp
.....\caiji.ise
.....\caiji.ise_ISE_Backup
.....\caiji.lso
.....\caiji.npl
.....\caiji.ntrc_log
.....\caiji.prj
.....\caiji.restore
.....\caiji.syr
.....\caiji.vhd
.....\caiji.xst
.....\caiji_summary.html
.....\caiji_vhdl.prj
.....\coregen.log
.....\coregen.prj
.....\jiekou.cmd_log
.....\jiekou.lso
.....\jiekou.prj
.....\jiekou.syr
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