Description: A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
- [10100MIP] - 10100M IP Ethernet core Verilog source c
- [vidicon] - vidicon s catch and collection in VHDL
- [Test] - Text to Speech VB
- [nfs_root_andriod.armv4.tar] - S3C2440 running at the android file syst
- [aes] - Advanced Encryption Standard AES, FPGA i
File list (Check if you may need any files):
memory_cores2\CVS\Entries
.............\...\Repository
.............\...\Root
.............\dpmem\core\CVS\Entries
.............\.....\....\...\Repository
.............\.....\....\...\Root
.............\.....\....\dpmem.vhd
.............\.....\....\WB_dpmem.vhd
.............\.....\CVS\Entries
.............\.....\...\Repository
.............\.....\...\Root
.............\fifo\core\CVS\Entries
.............\....\....\...\Repository
.............\....\....\...\Root
.............\....\....\fifo.vhd
.............\....\CVS\Entries
.............\....\...\Repository
.............\....\...\Root
.............\....\scripts\build_fifo.csh
.............\....\.......\CDS.LIB
.............\....\.......\.VS\Entries
.............\....\.......\...\Repository
.............\....\.......\...\Root
.............\....\tb\CVS\Entries
.............\....\..\...\Repository
.............\....\..\...\Root
.............\....\..\fifo_tb.vhd
.............\libs\CVS\Entries
.............\....\...\Repository
.............\....\...\Root
.............\....\memLib\CVS\Entries
.............\....\......\...\Repository
.............\....\......\...\Root
.............\....\......\mem_pkg.vhd
.............\....\tools_pkg.vhd
.............\.ut\CVS\Entries
.............\...\...\Repository
.............\...\...\Root
.............\...\lut.vhd
.............\spmem\core\CVS\Entries
.............\.....\....\...\Repository
.............\.....\....\...\Root
.............\.....\....\spmem.vhd
.............\.....\....\WB_spmem.vhd
.............\.....\CVS\Entries
.............\.....\...\Repository
.............\.....\...\Root
pci_core\Blocks\CVS\Entries
........\......\...\Repository
........\......\...\Root
........\......\pci_parity.vhd
........\CVS\Entries
........\...\Repository
........\...\Root
........\diagrams\CVS\Entries
........\........\...\Repository
........\........\...\Root
........\........\pci.dia
........\TestBench\CVS\Entries
........\.........\...\Repository
........\.........\...\Root
........\.........\pci_parity_tb.vhd
........\vhdl_behav\CVS\Entries
........\..........\...\Repository
........\..........\...\Root
........\..........\Ms32pci.vhd
........\..........\PCI.CMD
........\..........\Pci_lib.vhd
........\..........\readme.txt
........\..........\Test_pci.vhd
........\..........\Tg32pci.vhd
sdram_ctrl\CVS\Entries
..........\...\Repository
..........\...\Root
..........\doc\CVS\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\readme.txt
..........\...\sdram_ctrl.sxw
..........\src\CVS\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\sdram_ctrl.vhd
..........\.yn\CVS\Entries
..........\...\...\Repository
..........\...\...\Root
..........\...\sdram_ctrl\cb_generator.pl
..........\...\..........\class.ptf
..........\...\..........\CVS\Entries
..........\...\..........\...\Repository
..........\...\..........\...\Root
..........\...\..........\hdl\CVS\Entries
..........\...\..........\...\...\Repository
..........\...\..........\...\...\Root
..........\...\..........\...\sdram_ctrl.vhd
..........\test_bench\cpu_simulator.vhd
..........\..........\CVS\Entries
..........\..........\...\Repository
..........\..........\...\Root
..........\..........\mt48lc4m32b2.vhd
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