Description: 32 MIP pipelined CPU design, 5 stage, the code in detail, including the ALU, memory, registers, etc. is a very good CPU design
- [5_lined_cpu] - Simple line 5 of the CPU logic design ve
- [mipscpu-source] - mips cpu implementation. MIPS is the wor
- [ARM32ALU] - VHDL ARM 32 位 ALU design platform based
File list (Check if you may need any files):
mips_Pipeline\.recordref
.............\afg.jhd
.............\afg.tbw
.............\afg.udo
.............\afg.xwv
.............\afg.xwv_bak
.............\alu.prj
.............\alu.vhd
.............\alu_control.vhd
.............\alu_vhdl.prj
.............\asde.xwv
.............\asde.xwv_bak
.............\asdf.jhd
.............\asdf.tbw
.............\asdf.udo
.............\asdf.xwv
.............\asdf.xwv_bak
.............\automake.log
.............\control.vhd
.............\datapath.edn
.............\datapath.fse
.............\datapath.ncf
.............\datapath.prj
.............\datapath.sdc
.............\datapath.srd
.............\datapath.srm
.............\datapath.srr
.............\datapath.srs
.............\datapath.tbw
.............\datapath.vhd
.............\datapath.xwv
.............\datapath.xwv_bak
.............\datapath_compile.tcl
.............\datapath_map.tcl
.............\layer0.sro
.............\layer0.tlg
.............\mips_core.vhd
.............\mips_ram.vhd
.............\mips_rom.vhd
.............\mips_top.fse
.............\mips_top.ncf
.............\mips_top.prj
.............\mips_top.sdc
.............\mips_top.srd
.............\mips_top.srm
.............\mips_top.srr
.............\mips_top.srs
.............\mips_top.vhd
.............\mips_top_compile.tcl
.............\mips_top_map.tcl
.............\mips_top_summary.html
.............\mips_top_vhdl.prj
.............\newmips2.dhp
.............\newmips2.ise
.............\newmips2.ise_ISE_Backup
.............\pepExtractor.prj
.............\prjname.lso
.............\regestfile.vhd
.............\reg_t.jhd
.............\reg_t.tbw
.............\reg_t.udo
.............\reg_t.xwv
.............\reg_t.xwv_bak
.............\results.txt
.............\rpt_datapath.areasrr
.............\rpt_datapath_areasrr.htm
.............\rpt_mips_top.areasrr
.............\rpt_mips_top_areasrr.htm
.............\stderr.log
.............\stdout.log
.............\.yntmp\datapath.msg
.............\......\datapath.plg
.............\......\mips_top.msg
.............\......\mips_top.plg
.............\transcript
.............\traplog.tlg
.............\userlang.tpl
.............\verif\datapath.vif
.............\.....\mips_top.vif
.............\xst\work\hdllib.ref
.............\...\....\hdpdeps.ref
.............\...\....\sub00\vhpl00.vho
.............\...\....\.....\vhpl01.vho
.............\...\....\.....\vhpl02.vho
.............\...\....\.....\vhpl03.vho
.............\...\....\.....\vhpl04.vho
.............\...\....\.....\vhpl05.vho
.............\...\....\.....\vhpl06.vho
.............\...\....\.....\vhpl07.vho
.............\...\....\.....\vhpl08.vho
.............\...\....\.....\vhpl09.vho
.............\...\....\.....\vhpl10.vho
.............\...\....\.....\vhpl11.vho
.............\...\....\.....\vhpl12.vho
.............\...\....\.....\vhpl13.vho
.............\...\....\.....\vhpl14.vho
.............\...\....\.....\vhpl15.vho
.............\...\....\.....\vhpl16.vho
.............\...\....\.....\vhpl17.vho
.............\...\....\.....\vhpl18.vho
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