Description: This example application shows you how to use Real-Time Workshop Embedded Coder to target a dual core Blackfin microprocessor. The complete build is managed by a template makefile and control over the memory regions is provided by custom storage classes. The example imposes a top level architecture on the model to define the split of model code between the two cores. This document describes a complete run-through of the model from Simulink simulation to code simulation using VisualDSP. I think it will take about 1 hour to go through the example once you have VisualDSP installed.
File list (Check if you may need any files):
@Blackfin
.........\@CustomRTWInfo_Parameter
.........\........................\Blackfin_CustomRTWInfo_Parameter_Constructor.p
.........\........................\CustomRTWInfo_Parameter.p
.........\........................\CustomStorageClassListener.p
.........\........................\schema.p
.........\@CustomRTWInfo_Signal
.........\.....................\Blackfin_CustomRTWInfo_Signal_Constructor.p
.........\.....................\CustomRTWInfo_Signal.p
.........\.....................\CustomStorageClassListener.p
.........\.....................\schema.p
.........\@Dual
.........\.....\Blackfin_Dual_Constructor.p
.........\.....\Dual.p
.........\.....\schema.p
.........\csc_registration.m
.........\packagedefn.mat
.........\schema.p
.........\tlc
.........\...\BF561_FAST_L1_RAM.tlc
.........\...\BF561_SHARED_RAM.tlc
dsp_dual.tlc
dsp_dual.tmf
dual_basiccrt.doj
dual_core.mdl
dual_core_variables.m
expected_result.jpg
expected_result2.jpg
license.txt
readme.html
result.jpg
short_dos.jpg
toplevel.jpg
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