EMCRTL RTL Code for Design of Extarnal Memory Cont - CodeBus

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VHDL-FPGA-Verilog

Title: EMCRTL

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
5kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
wudalideepak

Description: RTL Code for Design of Extarnal Memory Controller for Accessing Asynchronous SRAM of size 512Kx16

Downloaders recently: [More information of uploader wudalideepak]

To Search: sram controller VHDL Memory Controller

[sram_controller] - sram controller implementation of the th
[memory_cores_latest[1].tar] - Memory controller
[del_ctrl] - A VHDL logical example of memory delay c

File list (Check if you may need any files):

EMCRTL
......\external_ram2.v
......\external_ram2_tb.v
......\IS61wv51216.v

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