Description: Verilog compiled fir filter, input parameters can be their own sequence, resulting in filtered waveforms
- [DDS_VERILOG] - the cases presented DDS VERIOG procedure
- [fir2] - Verilog prepared by the fir filter can a
- [8stepSymmetryCoefficientFilter] - 8-order FIR filter symmetric coefficient
- [digifilter.tar] - Verilog realize the digital filter for t
- [EDA] - There is a FIR filter design report ther
- [FIR_verilog] - Verilog based on the FIR filter, there a
- [FIR] - FPGA realization of digital filters, bas
- [18a] - Matched filter design, VERILOG implement
- [11FIRfliter] - 11-order FIR filter, and (7,4) encoder o
- [Verilog_Hdl48FIR] - verilog hdl fir
File list (Check if you may need any files):
fir_gen.v