ddr2_controller DDR2 controller design of the orig

Title: ddr2_controller

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
51kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
yanxp

Description: DDR2 controller design of the original code, can be tested through the FPGA, and external ddr memory read and write access.

Downloaders recently: [More information of uploader yanxp]

To Search: ddr2 ddr2 controller DDR2 controller desi ddr2 test bench DDR2 VHDL fpga ddr2 ddr memory controller vhdl ddr controller VHDL ddr controller

[zbt_rd_vhdl_str_v1.0.0] - ddr2 controller functions to control, wh
[DDR2Controller] - DDR2 Controller DDR2 Controller
[modelsim_ddr2sdram_spartan3s700an.tar] - Modelsim DDR2 SDRAM files
[edk_ctt] - a simple way to edk of xilinx
[amp] - This information is Xilinx' s IP for
[Xil3SD1800A_MIG_simplifiedUI_vlog_v92] - verilog achieved spartan 3A dsp start ki
[sdram_ver_134] - This code is a SDRAM Controller IP Core
[s3esk] - spartan 3e development board test routin
[mcb_read_write] - Xilinx DDR2 original user interface prog
[ddr_ddr2_sdram9.0] - altera provided ddr_ddr2_sdram9.0, DDR2

File list (Check if you may need any files):

ddr2_controller\dcm_0.v
...............\ddr2_spartan3a1400abank1fg676.v
...............\ddr2_spartan3a1400abank1fg676_addr_gen_0.v
...............\ddr2_spartan3a1400abank1fg676_cal_ctl_0.v
...............\ddr2_spartan3a1400abank1fg676_cal_top.v
...............\ddr2_spartan3a1400abank1fg676_clk_dcm.v
...............\ddr2_spartan3a1400abank1fg676_cmd_fsm_0.v
...............\ddr2_spartan3a1400abank1fg676_cmp_data_0.v
...............\ddr2_spartan3a1400abank1fg676_controller_0.v
...............\ddr2_spartan3a1400abank1fg676_controller_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_data_path_0.v
...............\ddr2_spartan3a1400abank1fg676_data_path_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_data_read_0.v
...............\ddr2_spartan3a1400abank1fg676_data_read_controller_0.v
...............\ddr2_spartan3a1400abank1fg676_data_write_0.v
...............\ddr2_spartan3a1400abank1fg676_dqs_delay.v
...............\ddr2_spartan3a1400abank1fg676_fifo_0_wr_en_0.v
...............\ddr2_spartan3a1400abank1fg676_fifo_1_wr_en_0.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_infrastructure_top_0.v
...............\ddr2_spartan3a1400abank1fg676_iobs_0.v
...............\ddr2_spartan3a1400abank1fg676_lfsr32_0.v
...............\ddr2_spartan3a1400abank1fg676_main_0.v
...............\ddr2_spartan3a1400abank1fg676_parameters_0.v
...............\ddr2_spartan3a1400abank1fg676_ram8d_0.v
...............\ddr2_spartan3a1400abank1fg676_rd_gray_cntr.v
...............\ddr2_spartan3a1400abank1fg676_s3_dm_iob_0.v
...............\ddr2_spartan3a1400abank1fg676_s3_dqs_iob.v
...............\ddr2_spartan3a1400abank1fg676_s3_dq_iob.v
...............\ddr2_spartan3a1400abank1fg676_tap_dly.v
...............\ddr2_spartan3a1400abank1fg676_test_bench_0.v
...............\ddr2_spartan3a1400abank1fg676_top_0.v
...............\ddr2_spartan3a1400abank1fg676_wr_gray_cntr.v
...............\ddr2_top.ucf
...............\ddr2_top.v
ddr2_controller

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