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Title: LAB_ATTEMPT2 Download
 Description: Verilog and SOPC implementation of interrupts for DE2 board and Cyclone II
 Downloaders recently: [More information of uploader jamieson]
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LAB_ATTEMPT2\APP_SOFTWARE
............\............\attempt2.s
............\attempt2.asm.rpt
............\attempt2.done
............\attempt2.dpf
............\attempt2.fit.rpt
............\attempt2.fit.smsg
............\attempt2.fit.summary
............\attempt2.flow.rpt
............\attempt2.jdi
............\attempt2.map.rpt
............\attempt2.map.smsg
............\attempt2.map.summary
............\attempt2.pin
............\attempt2.pof
............\attempt2.qpf
............\attempt2.qsf
............\attempt2.qsf.bak
............\attempt2.qws
............\attempt2.sof
............\attempt2.tan.rpt
............\attempt2.tan.summary
............\attempt2.v
............\attempt2.v.bak
............\cpu_0.sdc
............\cpu_0.v
............\cpu_0_jtag_debug_module_sysclk.v
............\cpu_0_jtag_debug_module_tck.v
............\cpu_0_jtag_debug_module_wrapper.v
............\cpu_0_oci_test_bench.v
............\cpu_0_ociram_default_contents.mif
............\cpu_0_rf_ram.mif
............\cpu_0_test_bench.v
............\db
............\..\a_dpfifo_8t21.tdf
............\..\a_fefifo_7cf.tdf
............\..\altsyncram_1l22.tdf
............\..\altsyncram_9tl1.tdf
............\..\altsyncram_c572.tdf
............\..\altsyncram_e502.tdf
............\..\altsyncram_f3c1.tdf
............\..\attempt2.asm.qmsg
............\..\attempt2.asm.rdb
............\..\attempt2.asm_labs.ddb
............\..\attempt2.cbx.xml
............\..\attempt2.cmp.bpm
............\..\attempt2.cmp.cdb
............\..\attempt2.cmp.ecobp
............\..\attempt2.cmp.hdb
............\..\attempt2.cmp.kpt
............\..\attempt2.cmp.logdb
............\..\attempt2.cmp.rdb
............\..\attempt2.cmp.tdb
............\..\attempt2.cmp_merge.kpt
............\..\attempt2.cmp0.ddb
............\..\attempt2.db_info
............\..\attempt2.eco.cdb
............\..\attempt2.fit.qmsg
............\..\attempt2.hier_info
............\..\attempt2.hif
............\..\attempt2.lpc.html
............\..\attempt2.lpc.rdb
............\..\attempt2.lpc.txt
............\..\attempt2.map.bpm
............\..\attempt2.map.cdb
............\..\attempt2.map.ecobp
............\..\attempt2.map.hdb
............\..\attempt2.map.kpt
............\..\attempt2.map.logdb
............\..\attempt2.map.qmsg
............\..\attempt2.map_bb.cdb
............\..\attempt2.map_bb.hdb
............\..\attempt2.map_bb.logdb
............\..\attempt2.pre_map.cdb
............\..\attempt2.pre_map.hdb
............\..\attempt2.rtlv.hdb
............\..\attempt2.rtlv_sg.cdb
............\..\attempt2.rtlv_sg_swap.cdb
............\..\attempt2.sgdiff.cdb
............\..\attempt2.sgdiff.hdb
............\..\attempt2.sld_design_entry.sci
............\..\attempt2.sld_design_entry_dsc.sci
............\..\attempt2.smart_action.txt
............\..\attempt2.smp_dump.txt
............\..\attempt2.syn_hier_info
............\..\attempt2.tan.qmsg
............\..\attempt2.tis_db_list.ddb
............\..\attempt2.tmw_info
............\..\cntr_fjb.tdf
............\..\cntr_rj7.tdf
............\..\dpram_5h21.tdf
............\..\logic_util_heursitic.dat
............\..\prev_cmp_attempt2.asm.qmsg
............\..\prev_cmp_attempt2.fit.qmsg
............\..\prev_cmp_attempt2.map.qmsg
............\..\prev_cmp_attempt2.qmsg
............\..\prev_cmp_attempt2.tan.qmsg
............\..\scfifo_1n21.tdf
............\..\sopcb_tb2_nios_system.xml
............\DE2_pin_assignments.csv
    

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