Description: Red Hurricane EP2C20 development board on the sdram details of the operation, which has made it clear documentation and routine analysis.
To Search:
- [fpga_ram_flash] - an fpga development board diagram, the b
- [RCII_V21_SCH] - Red Hurricane schematic, interested peop
- [EP3C25EVM] - cyclone III EP3C25 development board sch
- [SCHPCB] - Frequency of collection is based on the
- [AUDIO] - 这是红色飓风开发板基于NIOSII设计的音频采集与输出的完整工程,可以直接运行
File list (Check if you may need any files):
T4_sdram_control\doc\read_me.doc
................\...\SDRAM.doc
................\...\sdr_sdram.pdf
................\sim\altera_mf.v
................\...\Command.v
................\...\control_interface.v
................\...\mt48lc2m32b2.v
................\...\Params.v
................\...\sdram_test.cr.mti
................\...\sdram_test.mpf
................\...\sdram_test.wlf
................\...\sdram_test_tb.v
................\...\transcript
................\...\vsim.wlf
................\...\wave.do
................\...\.ork\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
................\...\....\..........................................\_primary.dat
................\...\....\..........................................\_primary.vhd
................\...\....\.m@f_pll_reg\verilog.asm
................\...\....\............\_primary.dat
................\...\....\............\_primary.vhd
................\...\....\.....ram7x20_syn\verilog.asm
................\...\....\................\_primary.dat
................\...\....\................\_primary.vhd
................\...\....\.....stratixii_pll\verilog.asm
................\...\....\..................\_primary.dat
................\...\....\..................\_primary.vhd
................\...\....\............_pll\verilog.asm
................\...\....\................\_primary.dat
................\...\....\................\_primary.vhd
................\...\....\alt3pram\verilog.asm
................\...\....\........\_primary.dat
................\...\....\........\_primary.vhd
................\...\....\...accumulate\verilog.asm
................\...\....\.............\_primary.dat
................\...\....\.............\_primary.vhd
................\...\....\...cam\verilog.asm
................\...\....\......\_primary.dat
................\...\....\......\_primary.vhd
................\...\....\....dr_rx\verilog.asm
................\...\....\.........\_primary.dat
................\...\....\.........\_primary.vhd
................\...\....\.......tx\verilog.asm
................\...\....\.........\_primary.dat
................\...\....\.........\_primary.vhd
................\...\....\....lklock\verilog.asm
................\...\....\..........\_primary.dat
................\...\....\..........\_primary.vhd
................\...\....\...ddio_bidir\verilog.asm
................\...\....\.............\_primary.dat
................\...\....\.............\_primary.vhd
................\...\....\........in\verilog.asm
................\...\....\..........\_primary.dat
................\...\....\..........\_primary.vhd
................\...\....\........out\verilog.asm
................\...\....\...........\_primary.dat
................\...\....\...........\_primary.vhd
................\...\....\....pram\verilog.asm
................\...\....\........\_primary.dat
................\...\....\........\_primary.vhd
................\...\....\...fp_mult\verilog.asm
................\...\....\..........\_primary.dat
................\...\....\..........\_primary.vhd
................\...\....\...lvds_rx\verilog.asm
................\...\....\..........\_primary.dat
................\...\....\..........\_primary.vhd
................\...\....\........tx\verilog.asm
................\...\....\..........\_primary.dat
................\...\....\..........\_primary.vhd
................\...\....\...mult_accum\verilog.asm
................\...\....\.............\_primary.dat
................\...\....\.............\_primary.vhd
................\...\....\.........dd\verilog.asm
................\...\....\...........\_primary.dat
................\...\....\...........\_primary.vhd
................\...\....\...pll\verilog.asm
................\...\....\......\_primary.dat
................\...\....\......\_primary.vhd
................\...\....\...qpram\verilog.asm
................\...\....\........\_primary.dat
................\...\....\........\_primary.vhd
................\...\....\...shift_taps\verilog.asm
................\...\....\.............\_primary.dat
................\...\....\.............\_primary.vhd
....
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