Description: Describes the digital voice communications, the use of in-system programmable technical and complex programmable logic device CPLD, to achieve the digital voice multiplexer and demultiplexer for the single steady state in which the digital circuit and digital phase locked loop extraction bit synchronization signals are also carried out a detailed design specification. The practical application results show that the system works stable and reliable design is successful.
- [1] - FPGA Synchronous design technology, quit
- [sheji2] - The hardware design of a stopwatch is us
- [CPLDfujie] - Digital reconnect is to combine two or m
- [yinpin] - The Superposition of the audio file is a
- [weitongbu] - failed to translate
- [sy2] - The oscillator frequency is 4.096 MHz, t
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用于多媒体通信的时分多路复用器的设计.pdf
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