SIGNAL_GEN The use of EDA, VHDL hardware descripti

Title: SIGNAL_GEN

Category:
VHDL-FPGA-Verilog
Tags:
File Size:
507kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
shuizi18

Description: The use of EDA, VHDL hardware description language design function of the signal generator can generate increased progressively decreasing ramp, triangle wave, step-wave, sine wave, square wave

Downloaders recently: [More information of uploader shuizi18]

To Search: square signal generator vhdl

[jietifangbo] - With counters to complete the ladder as
[SignalgeneratorinterfaceintheVirtualInstrumentDesi] - Signal generator virtual instrument inte
[signal] - written in verilog serial control signal
[fourkindofwavesproductedbyVHDL] - VHDL language with the signal generator.
[Quartus] - Prepared using vhdl source signal genera
[FINALWORK] - Simple signal generator can produce sine
[zuoye2] - Step square-wave generator
[DDS] - This is an arbitrary frequency sinusoida

File list (Check if you may need any files):

SIGNAL_GEN\CH41.bsf
..........\CH41.VHD
..........\DELTA.bsf
..........\DELTA.VHD
..........\DELTA.VHD.bak
..........\JIAN.bsf
..........\JIAN.VHD
..........\JIAN.VHD.bak
..........\LADDER.bsf
..........\LADDER.VHD
..........\LADDER.VHD.bak
..........\SIGNAL_GEN.asm.rpt
..........\SIGNAL_GEN.bdf
..........\SIGNAL_GEN.done
..........\SIGNAL_GEN.dpf
..........\SIGNAL_GEN.fit.rpt
..........\SIGNAL_GEN.fit.summary
..........\SIGNAL_GEN.flow.rpt
..........\SIGNAL_GEN.map.rpt
..........\SIGNAL_GEN.map.summary
..........\SIGNAL_GEN.pin
..........\SIGNAL_GEN.pof
..........\SIGNAL_GEN.qpf
..........\SIGNAL_GEN.qsf
..........\SIGNAL_GEN.qws
..........\SIGNAL_GEN.sim.rpt
..........\SIGNAL_GEN.sof
..........\SIGNAL_GEN.tan.rpt
..........\SIGNAL_GEN.tan.summary
..........\SIGNAL_GEN.vwf
..........\SIN.bsf
..........\SIN.VHD
..........\SIN.VHD.bak
..........\SQUARE.bsf
..........\SQUARE.VHD
..........\ZENG.bsf
..........\ZENG.VHD
..........\ZENG.VHD.bak
..........\db\add_sub_5nh.tdf
..........\..\add_sub_klh.tdf
..........\..\add_sub_mlh.tdf
..........\..\add_sub_olh.tdf
..........\..\add_sub_plh.tdf
..........\..\mux_1ac.tdf
..........\..\mux_mbc.tdf
..........\..\prev_cmp_SIGNAL_GEN.asm.qmsg
..........\..\prev_cmp_SIGNAL_GEN.fit.qmsg
..........\..\prev_cmp_SIGNAL_GEN.map.qmsg
..........\..\prev_cmp_SIGNAL_GEN.qmsg
..........\..\prev_cmp_SIGNAL_GEN.sim.qmsg
..........\..\prev_cmp_SIGNAL_GEN.tan.qmsg
..........\..\SIGNAL_GEN.asm.qmsg
..........\..\SIGNAL_GEN.cbx.xml
..........\..\SIGNAL_GEN.cmp.cdb
..........\..\SIGNAL_GEN.cmp.hdb
..........\..\SIGNAL_GEN.cmp.logdb
..........\..\SIGNAL_GEN.cmp.rdb
..........\..\SIGNAL_GEN.cmp.tdb
..........\..\SIGNAL_GEN.cmp0.ddb
..........\..\SIGNAL_GEN.dbp
..........\..\SIGNAL_GEN.db_info
..........\..\SIGNAL_GEN.eco.cdb
..........\..\SIGNAL_GEN.eds_overflow
..........\..\SIGNAL_GEN.fit.qmsg
..........\..\SIGNAL_GEN.fnsim.cdb
..........\..\SIGNAL_GEN.fnsim.hdb
..........\..\SIGNAL_GEN.fnsim.qmsg
..........\..\SIGNAL_GEN.hier_info
..........\..\SIGNAL_GEN.hif
..........\..\SIGNAL_GEN.map.cdb
..........\..\SIGNAL_GEN.map.hdb
..........\..\SIGNAL_GEN.map.logdb
..........\..\SIGNAL_GEN.map.qmsg
..........\..\SIGNAL_GEN.pre_map.cdb
..........\..\SIGNAL_GEN.pre_map.hdb
..........\..\SIGNAL_GEN.psp
..........\..\SIGNAL_GEN.pss
..........\..\SIGNAL_GEN.rtlv.hdb
..........\..\SIGNAL_GEN.rtlv_sg.cdb
..........\..\SIGNAL_GEN.rtlv_sg_swap.cdb
..........\..\SIGNAL_GEN.sgdiff.cdb
..........\..\SIGNAL_GEN.sgdiff.hdb
..........\..\SIGNAL_GEN.sim.cvwf
..........\..\SIGNAL_GEN.sim.hdb
..........\..\SIGNAL_GEN.sim.qmsg
..........\..\SIGNAL_GEN.sim.rdb
..........\..\SIGNAL_GEN.simfam
..........\..\SIGNAL_GEN.sld_design_entry.sci
..........\..\SIGNAL_GEN.sld_design_entry_dsc.sci
..........\..\SIGNAL_GEN.syn_hier_info
..........\..\SIGNAL_GEN.tan.qmsg
..........\..\SIGNAL_GEN.tis_db_list.ddb
..........\..\wed.wsf
..........\db
SIGNAL_GEN

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