Description: The use of VHDL in the Quartus II environment to realize VGA interface display control, display monochrome screen, color bars, checkerboard grid and so on.
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XIANGJIANLONG_S_VGA\db\altsyncram_lj71.tdf
...................\..\My_vga.asm.qmsg
...................\..\My_vga.asm_labs.ddb
...................\..\My_vga.cbx.xml
...................\..\My_vga.cmp.bpm
...................\..\My_vga.cmp.cdb
...................\..\My_vga.cmp.ecobp
...................\..\My_vga.cmp.hdb
...................\..\My_vga.cmp.logdb
...................\..\My_vga.cmp.rdb
...................\..\My_vga.cmp.tdb
...................\..\My_vga.cmp0.ddb
...................\..\My_vga.cmp2.ddb
...................\..\My_vga.db_info
...................\..\My_vga.eco.cdb
...................\..\My_vga.fit.qmsg
...................\..\My_vga.hier_info
...................\..\My_vga.hif
...................\..\My_vga.map.bpm
...................\..\My_vga.map.cdb
...................\..\My_vga.map.ecobp
...................\..\My_vga.map.hdb
...................\..\My_vga.map.logdb
...................\..\My_vga.map.qmsg
...................\..\My_vga.map_bb.cdb
...................\..\My_vga.map_bb.hdb
...................\..\My_vga.map_bb.hdbx
...................\..\My_vga.map_bb.logdb
...................\..\My_vga.pre_map.cdb
...................\..\My_vga.pre_map.hdb
...................\..\My_vga.psp
...................\..\My_vga.root_partition.cmp.atm
...................\..\My_vga.root_partition.cmp.dfp
...................\..\My_vga.root_partition.cmp.hdbx
...................\..\My_vga.root_partition.cmp.logdb
...................\..\My_vga.root_partition.cmp.rcf
...................\..\My_vga.root_partition.map.atm
...................\..\My_vga.root_partition.map.hdbx
...................\..\My_vga.root_partition.map.info
...................\..\My_vga.root_partition.merge_hb.atm
...................\..\My_vga.rtlv.hdb
...................\..\My_vga.rtlv_sg.cdb
...................\..\My_vga.rtlv_sg_swap.cdb
...................\..\My_vga.sgdiff.cdb
...................\..\My_vga.sgdiff.hdb
...................\..\My_vga.signalprobe.cdb
...................\..\My_vga.sld_design_entry.sci
...................\..\My_vga.sld_design_entry_dsc.sci
...................\..\My_vga.syn_hier_info
...................\..\My_vga.tan.qmsg
...................\..\My_vga.tis_db_list.ddb
...................\..\My_vga.tmw_info
...................\..\prev_cmp_My_vga.asm.qmsg
...................\..\prev_cmp_My_vga.fit.qmsg
...................\..\prev_cmp_My_vga.map.qmsg
...................\..\prev_cmp_My_vga.qmsg
...................\..\prev_cmp_My_vga.tan.qmsg
...................\My_vga.asm.rpt
...................\My_vga.bdf
...................\My_vga.bsf
...................\My_vga.cdf
...................\My_vga.done
...................\My_vga.dpf
...................\My_vga.fit.rpt
...................\My_vga.fit.smsg
...................\My_vga.fit.summary
...................\My_vga.flow.rpt
...................\My_vga.hexout
...................\My_vga.map.rpt
...................\My_vga.map.summary
...................\My_vga.pin
...................\My_vga.pof
...................\My_vga.qpf
...................\My_vga.qsf
...................\My_vga.qws
...................\My_vga.sof
...................\My_vga.tan.rpt
...................\My_vga.tan.summary
...................\My_vga.vhd
...................\My_vga.vhd.bak
...................\picture.bsf
...................\picture.cmp
...................\picture.qip
...................\picture.vhd
...................\picture_wave0.jpg
...................\picture_waveforms.html
...................\pll.bsf
...................\pll.cmp
...................\pll.ppf
...................\pll.qip
...................\pll.vhd
...................\pll_wave0.jpg
...................\pll_waveforms.html
...................\rom.mif
...................\vga.bsf
...................\vga.vhd
...................\vga.vhd.bak
...................\db
XIANGJIANLONG_S_VGA